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ZXMN2A04DN8TC-VB
Public Made by Adomby adom
VBsemi Elec MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ZXMN2A04DN8TC-VB
VBsemi Elec · MOSFETs · SO-8
ZXMN2A04DN8TC-VB from VBsemi Elec, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of MOSFET 1; MOSFET 1 is rated VDS 20 V, ID 7.1 A at TA = 25 °C. |
| 2 | G1 | input | Gate of MOSFET 1; gate-source voltage is limited to ±12 V. |
| 3 | S2 | passive | Source of MOSFET 2; MOSFET 2 is rated VDS 20 V, ID 7.1 A at TA = 25 °C. |
| 4 | G2 | input | Gate of MOSFET 2; gate-source voltage is limited to ±12 V. |
| 5 | D2 | passive | Drain of MOSFET 2; drain-source voltage is limited to 20 V, with pulsed drain current up to 40 A. |
| 6 | D2 | passive | Drain of MOSFET 2, internally tied to the other D2 pin; drain-source voltage is limited to 20 V. |
| 7 | D1 | passive | Drain of MOSFET 1; drain-source voltage is limited to 20 V, with pulsed drain current up to 40 A. |
| 8 | D1 | passive | Drain of MOSFET 1, internally tied to the other D1 pin; drain-source voltage is limited to 20 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | VBsemi Elec |
| Package | SO-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDS | 20 | V | 1 | |||
| Gate-Source Voltage | VGS | -12 | 12 | V | 1 | ||
| Continuous Drain Current | ID | 7.1 | A | TJ = 150 °C, TA = 25 °C | 1 | ||
| Continuous Drain Current | ID | 5.7 | A | TJ = 150 °C, TA = 70 °C | 1 | ||
| Pulsed Drain Current | IDM | 40 | A | 10 µs pulse width | 1 | ||
| Continuous Source Current (Diode Conduction) | IS | 1.7 | A | 1 | |||
| Maximum Power Dissipation | PD | 2 | W | TA = 25 °C | 1 | ||
| Maximum Power Dissipation | PD | 1.3 | W | TA = 70 °C | 1 | ||
| Operating Junction and Storage Temperature Range | TJ, Tstg | -55 | 150 | °C | 1 | ||
| Maximum Junction-to-Ambient | RthJA | 62.5 | °C/W | Surface Mounted on FR4 board, t ≤ 10 s | 1 | ||
| Gate Threshold Voltage | VGS(th) | 0.6 | 1.5 | V | VDS = VGS, ID = 250 µA | 2 | |
| Gate-Body Leakage | IGSS | -100 | 100 | nA | VDS = 0 V, VGS = ± 12 V | 2 | |
| Zero Gate Voltage Drain Current | IDSS | 1 | µA | VDS = 20 V, VGS = 0 V | 2 | ||
| Zero Gate Voltage Drain Current | IDSS | 5 | µA | VDS = 20 V, VGS = 0 V, TJ = 55 °C | 2 | ||
| On-State Drain Current | ID(on) | 20 | A | VDS ≥ 5 V, VGS = 4.5 V | 2 | ||
| Drain-Source On-State Resistance | RDS(on) | 0.019 | Ω | VGS = 4.5 V, ID = 7.1 A | 2 | ||
| Drain-Source On-State Resistance | RDS(on) | 0.026 | Ω | VGS = 2.5 V, ID = 6.0 A | 2 | ||
| Gate Resistance | Rg | 1.6 | 2.7 | Ω | f = 1 MHz | 2 | |
| Diode Forward Voltage | VSD | 1.2 | V | IS = 1.7 A, VGS = 0 V | 2 |
CAD (KiCad official)
- Symbol:
ZXMN2A04DN8TC-VB - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
zxmn2a04dn8tc-vb-etched.step/zxmn2a04dn8tc-vb-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);zxmn2a04dn8tc-vb.step/zxmn2a04dn8tc-vb.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: VBsemi Elec datasheet (7 pp, sha256
774f2212955c321a, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ZXMN2A04DN8TC-VB
**VBsemi Elec** · MOSFETs · SO-8
ZXMN2A04DN8TC-VB from VBsemi Elec, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of MOSFET 1; MOSFET 1 is rated VDS 20 V, ID 7.1 A at TA = 25 °C. |
| 2 | G1 | input | Gate of MOSFET 1; gate-source voltage is limited to ±12 V. |
| 3 | S2 | passive | Source of MOSFET 2; MOSFET 2 is rated VDS 20 V, ID 7.1 A at TA = 25 °C. |
| 4 | G2 | input | Gate of MOSFET 2; gate-source voltage is limited to ±12 V. |
| 5 | D2 | passive | Drain of MOSFET 2; drain-source voltage is limited to 20 V, with pulsed drain current up to 40 A. |
| 6 | D2 | passive | Drain of MOSFET 2, internally tied to the other D2 pin; drain-source voltage is limited to 20 V. |
| 7 | D1 | passive | Drain of MOSFET 1; drain-source voltage is limited to 20 V, with pulsed drain current up to 40 A. |
| 8 | D1 | passive | Drain of MOSFET 1, internally tied to the other D1 pin; drain-source voltage is limited to 20 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | VBsemi Elec |
| Package | SO-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDS | | | 20 | V | | 1 |
| Gate-Source Voltage | VGS | -12 | | 12 | V | | 1 |
| Continuous Drain Current | ID | | | 7.1 | A | TJ = 150 °C, TA = 25 °C | 1 |
| Continuous Drain Current | ID | | | 5.7 | A | TJ = 150 °C, TA = 70 °C | 1 |
| Pulsed Drain Current | IDM | | | 40 | A | 10 µs pulse width | 1 |
| Continuous Source Current (Diode Conduction) | IS | | | 1.7 | A | | 1 |
| Maximum Power Dissipation | PD | | | 2 | W | TA = 25 °C | 1 |
| Maximum Power Dissipation | PD | | | 1.3 | W | TA = 70 °C | 1 |
| Operating Junction and Storage Temperature Range | TJ, Tstg | -55 | | 150 | °C | | 1 |
| Maximum Junction-to-Ambient | RthJA | | | 62.5 | °C/W | Surface Mounted on FR4 board, t ≤ 10 s | 1 |
| Gate Threshold Voltage | VGS(th) | 0.6 | | 1.5 | V | VDS = VGS, ID = 250 µA | 2 |
| Gate-Body Leakage | IGSS | -100 | | 100 | nA | VDS = 0 V, VGS = ± 12 V | 2 |
| Zero Gate Voltage Drain Current | IDSS | | | 1 | µA | VDS = 20 V, VGS = 0 V | 2 |
| Zero Gate Voltage Drain Current | IDSS | | | 5 | µA | VDS = 20 V, VGS = 0 V, TJ = 55 °C | 2 |
| On-State Drain Current | ID(on) | 20 | | | A | VDS ≥ 5 V, VGS = 4.5 V | 2 |
| Drain-Source On-State Resistance | RDS(on) | | | 0.019 | Ω | VGS = 4.5 V, ID = 7.1 A | 2 |
| Drain-Source On-State Resistance | RDS(on) | | | 0.026 | Ω | VGS = 2.5 V, ID = 6.0 A | 2 |
| Gate Resistance | Rg | | 1.6 | 2.7 | Ω | f = 1 MHz | 2 |
| Diode Forward Voltage | VSD | | | 1.2 | V | IS = 1.7 A, VGS = 0 V | 2 |
## CAD (KiCad official)
- Symbol: `ZXMN2A04DN8TC-VB`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `zxmn2a04dn8tc-vb-etched.step` / `zxmn2a04dn8tc-vb-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `zxmn2a04dn8tc-vb.step` / `zxmn2a04dn8tc-vb.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [VBsemi Elec datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603048208428126208) (7 pp, sha256 `774f2212955c321a`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/zxmn2a04dn8tc-vb-datasheet.pdf)