component
ZXGD3113W6-7
Public Made by Adomby adom
Diodes Incorporated Pre-ordered Chips, SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownZXGD3113W6-7
Diodes Incorporated · Pre-ordered Chips · SOT-23-6
ZXGD3113W6-7 from Diodes Incorporated, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | REF | input | Reference pin connected to VCC via resistor RREF, which sets the source current into this pin (RREF ≈ (VCC - 0.7)/IREF, max IREF 25 mA). |
| 2 | BIAS | input | Bias pin connected to VCC via resistor RBIAS, which sets the source current into this pin (RBIAS ≈ (VCC - 0.5)/IBIAS, max IBIAS 100 mA). |
| 3 | VCC | power_in | Supply pin (3.5V to 40V range, 40 V absolute maximum) that should be decoupled closely to ground with a ceramic capacitor. |
| 4 | GATE | output | Gate drive pin that sources and sinks current to and from the synchronous MOSFET gate (peak source 1.5 A, peak sink 3 A absolute max). |
| 5 | GND | power_in | Ground reference point, connected to the synchronous MOSFET Source terminal. |
| 6 | DRAIN | input | Drain sense pin connected to the Drain of the synchronous MOSFET, with voltage range of -3 V to 160 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SOT-23-6 |
| Category | Interface ICs |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage, Relative to GND | VCC | 40 | V | 3 | |||
| Drain Pin Voltage | VD | -3 | 160 | V | 3 | ||
| Gate Output Voltage | VG | -3 | V | -3 to VCC +3 | 3 | ||
| Gate Driver Peak Source Current | ISOURCE | 1.5 | A | 3 | |||
| Gate Driver Peak Sink Current | ISINK | 3 | A | 3 | |||
| Reference Current | IREF | 25 | mA | 3 | |||
| Bias Current | IBIAS | 100 | mA | 3 | |||
| Power Dissipation | PD | 500 | mW | Note 5 | 3 | ||
| Power Dissipation | PD | 731 | mW | Note 6 | 3 | ||
| Power Dissipation | PD | 868 | mW | Note 7 | 3 | ||
| Power Dissipation | PD | 1016 | mW | Note 8 | 3 | ||
| Thermal Resistance, Junction to Ambient | RθJA | 250 | °C/W | Note 5 | 3 | ||
| Thermal Resistance, Junction to Ambient | RθJA | 171 | °C/W | Note 6 | 3 | ||
| Thermal Resistance, Junction to Ambient | RθJA | 144 | °C/W | Note 7 | 3 | ||
| Thermal Resistance, Junction to Ambient | RθJA | 123 | °C/W | Note 8 | 3 | ||
| Thermal Resistance, Junction to Lead | RθJL | 105 | °C/W | Note 9 | 3 | ||
| Operating Temperature Range | TJ | -40 | 150 | °C | 3 | ||
| Storage Temperature Range | TSTG | -55 | 150 | °C | 3 | ||
| Quiescent Current | IQ | 6.2 | mA | VD ≥ 0V; VCC = 19V; RBIAS = 4.7kΩ; RREF = 8.2kΩ | 4 | ||
| Turn-Off Threshold Voltage | VT | -20 | -10 | 0 | mV | VG = 1V | 4 |
| Gate Output Voltage (off) | VG(OFF) | 0 | 0.73 | 1 | V | VD ≥ 1V | 4 |
| Gate Output Voltage | VG | 12.5 | 13.8 | V | VD = -50mV (max printed as VCC) | 4 | |
| Gate Output Voltage | VG | 17 | 17.8 | V | VD = -100mV (max printed as VCC) | 4 | |
| Turn-On Propagation Delay | tD(RISE) | 250 | ns | CLOAD = 10nF | 4 | ||
| Turn-Off Propagation Delay | tD(FALL) | 27 | ns | CLOAD = 10nF | 4 | ||
| Gate Rise Time | tR | 187 | ns | From 10% of VG to 10V | 4 | ||
| Gate Rise Time | tR | 360 | ns | From 10% to 90% of VG | 4 | ||
| Gate Fall Time | tF | 210 | ns | From 90% to 10% of VG | 4 | ||
| Source Current | ISOURCE | 0.5 | A | Capacitive Load of 10nF | 4 | ||
| Sink Current | ISINK | 1.5 | A | Capacitive Load of 10nF | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | Terminals: Matte Tin Finish, Solderable per MIL-STD-202, Method 208 | 1 |
CAD (KiCad official)
- Symbol:
ZXGD3113W6-7 - Footprint:
Package_TO_SOT_SMD:SOT-23-6 - 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
zxgd3113w6-7-etched.step/zxgd3113w6-7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);zxgd3113w6-7.step/zxgd3113w6-7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Diodes Incorporated datasheet (8 pp, sha256
9669f4538b4820ad, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).