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Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	ztp7106t: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	5d ago
viewers	pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray	1mo ago
package.json	pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray	1mo ago
pads.json	pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray	1mo ago
page.json	ztp7106t: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray	20h ago
README.md	ztp7106t: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray	19d ago
ztp7106t-etched.fit.json	ztp7106t: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	5d ago
ztp7106t-etched.glb	ztp7106t: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	5d ago
ztp7106t-etched.step	ztp7106t: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	5d ago
ztp7106t.glb	Publish 0.1.0 · Ray	1mo ago
ztp7106t.kicad_mod	Publish 0.1.0 · Ray	1mo ago
ztp7106t.kicad_sym	Publish 0.1.0 · Ray	1mo ago
ztp7106t.lbr	rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect and oval pad as a SQUARE EAGLE smd; this carries the real pad shape across (0 -> 5 rounded pads) and stops dropping geometry drawn on KiCad User.N layers. Attributes, connects, pads and the pin-1 marker are gated against decreasing and are unchanged. · Ray	1mo ago
ztp7106t.step	Publish 0.1.0 · Ray	1mo ago

ZTP7106T

ZILLTEK · DC-DC Converters · TSOT-23-5L

ZTP7106T from ZILLTEK, in a TSOT-23-5L. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	EN	input	Enable control input. Drive high (VENH >= 1.5V) to enable the converter; drive low (VENL <= 0.4V) to shut down the device (shutdown current < 1µA). EN input current is +/-1µA over 0V to Vin.
2	GND	power_in	Device ground return. Also the case position used for TSOT23-5 θJC measurement; connect to the ground plane with a low-impedance path.
3	SW	output	Power switch output. Common drain of the internal PMOS (UG) and NMOS (LG) power FETs; connect to the external inductor (2.2µH typ). Absolute max range -0.3V to Vin+0.3V; SW peak current 3A max; PMOS current limit typ 2A.
4	Vin	power_in	Main supply input, 2.5V to 5.5V. Bypass to GND with a 4.7µF ceramic (X5R/X7R) capacitor placed close to the pin. Absolute max 6V.
5	FB	input	Feedback input to the internal error amplifier. Regulates to VREF = 0.6V (0.588V/0.612V min/max); set Vout with a resistor divider from Vout to FB to GND: Vout = 0.6V x (1 + R1/R2). A small feed-forward capacitor (10-47pF, 22pF typical) in parallel with R1 speeds up transient response.

Key specifications

Parameter	Value
Manufacturer	ZILLTEK
Package	TSOT-23-5L
Category	PMIC
Pins	5

Ordering variants

Same part, different packaging or reel option.

ZTP7106TT
ZTP7106TD

CAD (KiCad official)

Symbol: ZTP7106T
Footprint: Package_TO_SOT_SMD:SOT-23-5
3D model: TSOT-23-5L (KiCad packages3D, STEP)
3D model files: ztp7106t-etched.step / ztp7106t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ztp7106t.step / ztp7106t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: ZILLTEK datasheet (8 pp, sha256 b898fa584d53b5c5, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF