component
ZTP7106T
Public Made by Adomby adom
ZILLTEK DC-DC Converters, TSOT-23-5L. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
ztp7106t: backfill missing artifacts (etch, variants)
3 files changed
+22843−6
diff truncated
README.md+2@@ -25,6 +25,8 @@ ZTP7106T from ZILLTEK, in a TSOT-23-5L. Pinout and pin descriptions extracted fr ## Ordering variants +Same part, different packaging or reel option.+ - `ZTP7106TT` - `ZTP7106TD`
page.json+17−6@@ -34,25 +34,25 @@ "number": "1", "name": "EN", "type": "input",- "description": "Enable control input. Drive high (VENH >= 1.5V) to enable the converter; drive low (VENL <= 0.4V) to shut down the device (shutdown current < 1\u00b5A). EN input current is +/-1\u00b5A over 0V to Vin."+ "description": "Enable control input. Drive high (VENH >= 1.5V) to enable the converter; drive low (VENL <= 0.4V) to shut down the device (shutdown current < 1µA). EN input current is +/-1µA over 0V to Vin." }, { "number": "2", "name": "GND", "type": "power_in",- "description": "Device ground return. Also the case position used for TSOT23-5 \u03b8JC measurement; connect to the ground plane with a low-impedance path."+ "description": "Device ground return. Also the case position used for TSOT23-5 θJC measurement; connect to the ground plane with a low-impedance path." }, { "number": "3", "name": "SW", "type": "output",- "description": "Power switch output. Common drain of the internal PMOS (UG) and NMOS (LG) power FETs; connect to the external inductor (2.2\u00b5H typ). Absolute max range -0.3V to Vin+0.3V; SW peak current 3A max; PMOS current limit typ 2A."+ "description": "Power switch output. Common drain of the internal PMOS (UG) and NMOS (LG) power FETs; connect to the external inductor (2.2µH typ). Absolute max range -0.3V to Vin+0.3V; SW peak current 3A max; PMOS current limit typ 2A." }, { "number": "4", "name": "Vin", "type": "power_in",- "description": "Main supply input, 2.5V to 5.5V. Bypass to GND with a 4.7\u00b5F ceramic (X5R/X7R) capacitor placed close to the pin. Absolute max 6V."+ "description": "Main supply input, 2.5V to 5.5V. Bypass to GND with a 4.7µF ceramic (X5R/X7R) capacitor placed close to the pin. Absolute max 6V." }, { "number": "5",@@ -132,9 +132,20 @@ "docs/hero.png", "docs/ztp7106t-datasheet.pdf", "viewers/symbol.html",- "viewers/footprint.html"+ "viewers/footprint.html",+ "ztp7106t-etched.step" ], "visibility": { "public": true- }+ },+ "variants": [+ {+ "mpn": "ZTP7106TT",+ "kind": "packaging"+ },+ {+ "mpn": "ZTP7106TD",+ "kind": "packaging"+ }+ ] }
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SPACE',''+ ) );+#13166 = PCURVE('',#13167,#13172);+#13167 = PLANE('',#13168);+#13168 = AXIS2_PLACEMENT_3D('',#13169,#13170,#13171);+#13169 = CARTESIAN_POINT('',(-1.4,-1.2,0.15));+#13170 = DIRECTION('',(0.,0.,-1.));+#13171 = DIRECTION('',(1.,-1.144237745222E-17,0.));+#13172 = DEFINITIONAL_REPRESENTATION('',(#13173),#13177);+#13173 = LINE('',#13174,#13175);+#13174 = CARTESIAN_POINT('',(-5.72118872611E-18,-0.5));+#13175 = VECTOR('',#13176,1.);+#13176 = DIRECTION('',(1.,0.));+#13177 = ( GEOMETRIC_REPRESENTATION_CONTEXT(2) +PARAMETRIC_REPRESENTATION_CONTEXT() REPRESENTATION_CONTEXT('2D SPACE',''+ ) );+#13178 = ORIENTED_EDGE('',*,*,#13179,.T.);+#13179 = EDGE_CURVE('',#13152,#13180,#13182,.T.);+#13180 = VERTEX_POINT('',#13181);+#13181 = CARTESIAN_POINT('',(-1.172050016982,-0.7,0.232635182233));+#13182 = SURFACE_CURVE('',#13183,(#13188,#13199),.PCURVE_S1.);+#13183 = CIRCLE('',#13184,0.1);+#13184 = AXIS2_PLACEMENT_3D('',#13185,#13186,#13187);+#13185 = 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CURVE() GEOMETRIC_REPRESENTATION_ITEM() +RATIONAL_B_SPLINE_CURVE((1.,0.5,1.,0.5,1.,0.5,1.)) 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CURVE() GEOMETRIC_REPRESENTATION_ITEM() +RATIONAL_B_SPLINE_CURVE((1.,0.5,1.,0.5,1.,0.5,1.)) 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