component
ZTP7001T-00
Public Made by Adomby adom
ZILLTEK Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, TSOT-23-5L. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ZTP7001T-00
ZILLTEK · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · TSOT-23-5L
ZTP7001T-00 from ZILLTEK, in a TSOT-23-5L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Input voltage, operating range 1.65V to 5.5V; connect a minimum 1uF ceramic capacitor to this pin for stable operation. |
| 2 | GND | power_in | Ground reference pin for the regulator. |
| 3 | EN | input | Active-high chip enable with a VIH minimum of 1.6V and VIL maximum of 0.4V; it is internally pulled down by a 1uA current source, and a logic low shuts down the output. |
| 4 | FB | input | Output voltage feedback input, regulated to 0.8V (VFB 784mV to 816mV at 10mA); connect a resistive divider between VOUT and FB to set the output voltage. |
| 5 | VOUT | power_out | Regulated output voltage; connect a minimum 1uF ceramic capacitor for stable operation, and the pin is discharged to ground through an internal 100Ω MOSFET when the chip is disabled or thermal protection is triggered. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ZILLTEK |
| Package | TSOT-23-5L |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Supply Voltage | VIN | -0.3 | 6 | V | 2 | ||
| Voltage at EN | -0.3 | 6 | V | 2 | |||
| Others (voltage at other pins) | -0.3 | V | 2 | ||||
| Maximum Power Dissipation | PD | 0.4 | W | TA = 25°C | 2 | ||
| Junction Temperature | 150 | °C | 2 | ||||
| ESD (Human Body Mode) | 2 | kV | Human Body Mode | 2 | |||
| ESD (Machine Mode) | 200 | V | Machine Mode | 2 | |||
| Continuous Junction Temperature | -40 | 125 | °C | 3 | |||
| Ambient Temperature Range | -40 | 85 | °C | 3 | |||
| Input Voltage Range | 1.65 | 5.5 | V | 3 | |||
| Input Supply Voltage | VIN | 1.65 | 5.5 | V | 3 | ||
| VIN Under Voltage Lockout | VUVLO | 1.5 | 1.6 | V | 3 | ||
| Shutdown Current | ISD | 1 | uA | VEN = 0V | 3 | ||
| Maximum Output Current | IOUT | 600 | 800 | mA | 3 | ||
| Load Regulation | ∆VOUT/∆IOUT | 30 | 50 | mV | 1mA < IOUT < 600mA | 3 | |
| FB Pin Voltage | VFB | 784 | 800 | 816 | mV | IOUT = 10mA | 3 |
| EN Input High Threshold | VIH | 1.6 | V | 3 | |||
| EN Input Low Threshold | VIL | 0.4 | V | 3 | |||
| Thermal Resistance, junction to ambient (datasheet headline value) | θJA | 250 | °C/W | 2 | |||
| Thermal Resistance, junction to case | θJC | 25 | °C/W | 2 | |||
| Measured Thermal Resistance, junction to ambient (2-layer board) | θJA | 125 | °C/W | Copper area 2500 mm2, board area 2500 mm2, 2-layer | 7 | ||
| Measured Thermal Resistance, junction to ambient (2-layer board) | θJA | 130 | °C/W | Copper area 225 mm2, board area 2500 mm2, 2-layer | 7 | ||
| Measured Thermal Resistance, junction to ambient (2-layer board) | θJA | 135 | °C/W | Copper area 100 mm2, board area 2500 mm2, 2-layer | 7 | ||
| Measured Thermal Resistance, junction to ambient (2-layer board) | θJA | 150 | °C/W | Copper area 50 mm2, board area 2500 mm2, 2-layer | 7 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | the copper lead frame, through the package (especially | 7 |
CAD (KiCad official)
- Symbol:
ZTP7001T-00 - Footprint:
Package_TO_SOT_SMD:TSOT-23-5 - 3D model: TSOT-23-5L (KiCad packages3D, STEP)
- 3D model files:
ztp7001t-00-etched.step/ztp7001t-00-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ztp7001t-00.step/ztp7001t-00.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ZILLTEK datasheet (9 pp, sha256
6e3c9807aa66045f, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ZTP7001T-00
**ZILLTEK** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · TSOT-23-5L
ZTP7001T-00 from ZILLTEK, in a TSOT-23-5L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Input voltage, operating range 1.65V to 5.5V; connect a minimum 1uF ceramic capacitor to this pin for stable operation. |
| 2 | GND | power_in | Ground reference pin for the regulator. |
| 3 | EN | input | Active-high chip enable with a VIH minimum of 1.6V and VIL maximum of 0.4V; it is internally pulled down by a 1uA current source, and a logic low shuts down the output. |
| 4 | FB | input | Output voltage feedback input, regulated to 0.8V (VFB 784mV to 816mV at 10mA); connect a resistive divider between VOUT and FB to set the output voltage. |
| 5 | VOUT | power_out | Regulated output voltage; connect a minimum 1uF ceramic capacitor for stable operation, and the pin is discharged to ground through an internal 100Ω MOSFET when the chip is disabled or thermal protection is triggered. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ZILLTEK |
| Package | TSOT-23-5L |
| Category | Power Management (PMIC) |
| Pins | 5 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Supply Voltage | VIN | -0.3 | | 6 | V | | 2 |
| Voltage at EN | | -0.3 | | 6 | V | | 2 |
| Others (voltage at other pins) | | -0.3 | | | V | | 2 |
| Maximum Power Dissipation | PD | | | 0.4 | W | TA = 25°C | 2 |
| Junction Temperature | | | | 150 | °C | | 2 |
| ESD (Human Body Mode) | | | | 2 | kV | Human Body Mode | 2 |
| ESD (Machine Mode) | | | | 200 | V | Machine Mode | 2 |
| Continuous Junction Temperature | | -40 | | 125 | °C | | 3 |
| Ambient Temperature Range | | -40 | | 85 | °C | | 3 |
| Input Voltage Range | | 1.65 | | 5.5 | V | | 3 |
| Input Supply Voltage | VIN | 1.65 | | 5.5 | V | | 3 |
| VIN Under Voltage Lockout | VUVLO | | 1.5 | 1.6 | V | | 3 |
| Shutdown Current | ISD | | | 1 | uA | VEN = 0V | 3 |
| Maximum Output Current | IOUT | 600 | 800 | | mA | | 3 |
| Load Regulation | ∆VOUT/∆IOUT | | 30 | 50 | mV | 1mA < IOUT < 600mA | 3 |
| FB Pin Voltage | VFB | 784 | 800 | 816 | mV | IOUT = 10mA | 3 |
| EN Input High Threshold | VIH | 1.6 | | | V | | 3 |
| EN Input Low Threshold | VIL | | | 0.4 | V | | 3 |
| Thermal Resistance, junction to ambient (datasheet headline value) | θJA | | 250 | | °C/W | | 2 |
| Thermal Resistance, junction to case | θJC | | 25 | | °C/W | | 2 |
| Measured Thermal Resistance, junction to ambient (2-layer board) | θJA | | 125 | | °C/W | Copper area 2500 mm2, board area 2500 mm2, 2-layer | 7 |
| Measured Thermal Resistance, junction to ambient (2-layer board) | θJA | | 130 | | °C/W | Copper area 225 mm2, board area 2500 mm2, 2-layer | 7 |
| Measured Thermal Resistance, junction to ambient (2-layer board) | θJA | | 135 | | °C/W | Copper area 100 mm2, board area 2500 mm2, 2-layer | 7 |
| Measured Thermal Resistance, junction to ambient (2-layer board) | θJA | | 150 | | °C/W | Copper area 50 mm2, board area 2500 mm2, 2-layer | 7 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | | the copper lead frame, through the package (especially | 7 |
## CAD (KiCad official)
- Symbol: `ZTP7001T-00`
- Footprint: `Package_TO_SOT_SMD:TSOT-23-5`
- 3D model: TSOT-23-5L (KiCad packages3D, STEP)
- 3D model files: `ztp7001t-00-etched.step` / `ztp7001t-00-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ztp7001t-00.step` / `ztp7001t-00.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [ZILLTEK datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603388693201625088) (9 pp, sha256 `6e3c9807aa66045f`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ztp7001t-00-datasheet.pdf)