component
ZSC31050FAG1-T
Public Made by Adomby adom
RENESAS Interface - Specialized, SSOP-16-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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ZSC31050FAG1-T
RENESAS · Interface - Specialized · SSOP-16-208mil
ZSC31050FAG1-T from RENESAS, in a SSOP-16-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDDA | power_in | Positive analog supply voltage, the supply pin for the analog front end. |
| 2 | IN3 | input | Resistive temperature sensor input and external clock input; freely accessible, but vulnerable to latch-up if the section 4 limits (±100 mA or +8 V/-4 V relative to VSS) are exceeded. |
| 3 | VGATE | output | Gate voltage output for the external regulator FET; the only permitted connection is to an external JFET. |
| 4 | IO1 | bidirectional | Flexible digital I/O carrying SPI data out, ALARM1 or PWM1 output; freely accessible by the application. |
| 5 | IO2 | bidirectional | Flexible digital I/O carrying SPI slave select or ALARM2; freely accessible by the application. |
| 6 | SCL | input | I2C clock or SPI clock input with pull-up; freely accessible by the application. |
| 7 | SDA | bidirectional | Data I/O for I2C or data input for SPI, with pull-up; freely accessible by the application. |
| 8 | VDD | power_in | Positive digital supply voltage; only a capacitor to VSS is allowed, otherwise there is no application access. |
| 9 | FBN | passive | Negative feedback connection for the output stage; freely accessible by the application. |
| 10 | OUT | bidirectional | Analog output, PWM2 output or one-wire interface (ZACwire) I/O; freely accessible by the application. |
| 11 | FBP | passive | Positive feedback connection for the output stage; freely accessible by the application. |
| 12 | IR_TEMP | passive | Current source resistor I/O and temperature diode input; circuitry keeps the potential within VSS-VDDA, otherwise there is no application access. |
| 13 | VBR | passive | Bridge top sensing input and bridge current output; only a short to VDDA or a connection to the sensor bridge is allowed, otherwise there is no application access. |
| 14 | VINP | input | Positive input from the sensor bridge; freely accessible by the application. |
| 15 | VSS | power_in | Negative supply voltage, the ground reference for the device. |
| 16 | VINN | input | Negative input from the sensor bridge; freely accessible by the application. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | SSOP-16-208mil |
| Category | Interface ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Digital supply voltage | VDDMAX | -0.3 | 6.5 | V DC | To VSS | 5 | |
| Analog supply voltage | VDDAMAX | -0.3 | 6.5 | V DC | To VSS | 5 | |
| Voltage at all analog and digital I/O pins | VA_I/O, VD_I/O | -0.3 | V DC | Except FBP, SDA, SCL (see 1.1.4, 1.1.5, 1.1.6) | 5 | ||
| Voltage at FBP pin | VFBP_MAX | -1.2 | V DC | 4mA to 20mA, Interface | 5 | ||
| Voltage at SDA pin | VSDA_MAX | -0.3 | 5.5 | V DC | I2C mode only | 5 | |
| Storage temperature | TSTG | -45 | 150 | °C | 5 | ||
| Ambient temperature range for part numbers ZSC31050xAxx | TAMB_TQA | -40 | 125 | °C | 5 | ||
| Ambient temperature EEPROM programming | TAMB_EEP | -25 | 85 | °C | 5 | ||
| EEPROM programming cycles | 100 | 5 | |||||
| Data retention (EEPROM) | 15 | years | Average temp. < 85°C | 5 | |||
| Analog supply voltage | VDDA | 2.7 | 5.5 | V DC | Ratiometric mode | 6 | |
| Analog supply voltage advanced performance | VDDAADV | 4.5 | 5.5 | V DC | Ratiometric mode | 6 | |
| Common-mode input range | VIN_CM | 0.21 | 0.76 | VADC_REF | Depends on gain adjust; refer to section 2.3.1 | 6 | |
| Sensor bridge resistance (over full temperature range) | RBR | 3 | 25 | kΩ | over full temperature range | 6 | |
| Sensor bridge resistance, current loop interface | RBR_CL | 5 | 25 | kΩ | Current loop interface, 4 to 20mA | 6 | |
| Stabilization capacitor | CVDDA | 50 | 100 | 470 | nF | External capacitor between VDDA and VSS | 6 |
| VDD stabilization capacitor | CVDD | 0 | 100 | 470 | nF | Between VDD and VSS, external | 6 |
| Maximum load capacitance allowed at OUT | CL_OUT | 50 | nF | Output Voltage Mode | 6 | ||
| Minimum load resistance allowed | RL_OUT | 2 | kΩ | Output Voltage Mode | 6 | ||
| Maximum load capacitance allowed at VGATE | CL_VGATE | 10 | nF | Total capacitance relative to all potentials | 6 | ||
| Selectable input span, bridge sensor measurement | VIN_SP | 2 | 280 | mV/V | Refer to section 2.3.1 | 7 | |
| Analog offset compensation range (6 bit setting) | -20 | 20 | Counts | 6 bit setting | 7 | ||
| Maximum bias current | -25 | 25 | Counts | Maximum bias current [a] | 7 | ||
| Analog-to-digital conversion (ADC) resolution | rADC | 9 | 15 | Bits | 3-bit setting [b] | 7 | |
| ADC input range | 10 | 90 | %VDDA | Range | 7 | ||
| Digital-to-analog conversion (DAC) resolution | rDAC | 11 | Bits | At analog output | 7 | ||
| PWM resolution | rPWM | 9 | 12 | Bits | 7 | ||
| Bias current for external temperature diodes | ITS | 8 | 18 | 40 | µA | 7 | |
| Sensitivity internal temperature diode | STT_SI | 2800 | 3200 | 3600 | ppm FS/K | Raw values without conditioning | 7 |
| Clock frequency | fCLK | 1 | 2 | 4 | MHz | Guaranteed adjustment range | 7 |
| Supply current | ISUPP | 2.5 | 4 | mA | Without bridge and load current, bias adjustment ≤ 4, fCLK ≤ 2.4MHz | 9 | |
| Supply current for current loop | ISUPP_CL | 2 | 2.75 | mA | Without bridge current, fCLK ≤ 1.2MHz, bias adjustment ≤ 1 | 9 | |
| Temperature coefficient voltage reference | TCREF | -200 | 50 | 200 | ppm/K | 9 | |
| Parasitic differential input offset current | IIN_OFF | -10 | 10 | nA | Temperature range = TAMB_TQI (-40 to 85°C) | 9 | |
| Output signal range | VOUT_SR | 0.025 | 0.975 | VDDA | Voltage Mode, RLOAD > 2KΩ; VDDAADV; Temperature range = TAMB_TQI | 9 | |
| Output DNL | DNLOUT | 0.95 | LSB | VDDAADV; Temperature range = TAMB_TQI | 9 | ||
| Output INL | INLOUT | 4 | LSB | 9 | |||
| Output slew rate | SROUT | 0.1 | V/µs | Voltage Mode; load capacitance < 20nF; using conditions of 1.4.3.1 | 9 | ||
| Short circuit current | IOUT_max | 5 | 10 | 20 | mA | 9 | |
| Addressable output signal range | VOUT_ADR | 0 | 1 | VDDA | 2048 steps | 9 | |
| PWM high voltage | VPWM_H | 0.9 | VDDA | Load resistance > 10kΩ | 9 | ||
| PWM low voltage | VPWM_L | 0.1 | VDDA | Load resistance > 10kΩ | 9 | ||
| PWM output slew rate | SRPWM | 15 | V/µs | Load capacitance < 1nF | 9 | ||
| Sensitivity external diode / resistor measurement | STTS_E | 75 | 210 | µV/LSB | At rADC = 13 bits | 9 | |
| Output high level | VDOUT_H | 0.9 | VDDA | Load resistance > 1 kΩ | 10 | ||
| Output low level | VDOUT_L | 0.1 | VDDA | Load resistance > 1 kΩ | 10 | ||
| Startup time | tSTA | 2 | 5 | ms | Power-on to 1st measurement result at output | 10 | |
| Response time | tRESP | 1.66 | 2.66 | 3.66 | 1/fCON | 66% change in input signal; refer to Table 3 for fCON | 10 |
| Overall accuracy (deviation from ideal line including INL, gain, and offset errors) | ACOUT | 0.25 | % | TAMB_TQA (-40 to 125 °C) & VDDAADV | 10 | ||
| Analog output noise peak-to-peak | VNOISE_PP | 10 | mV | Shorted inputs, gain ≤ 210, bandwidth ≤ 10kHz | 10 | ||
| Analog output noise RMS | VNOISE_RMS | 3 | mV | Shorted inputs, gain ≤ 210, bandwidth ≤ 10kHz | 10 | ||
| Ratiometricity error (5V) | REOUT_5V | 1000 | ppm | ±5% | 10 | ||
| Ratiometricity error (3V) | REOUT_3V | 200 | ppm | ±5% | 10 | ||
| Multiport serial interface input high level | VI2C_IN_H | 0.7 | 1 | VDDA | I2C mode; see footnote [a] (max 5.5 V DC independent of VDDA) | 11 | |
| Multiport serial interface input low level | VI2C_IN_L | 0 | 0.3 | VDDA | 11 | ||
| Load capacitance at the SDA pin | CSDA | 400 | pF | 11 | |||
| Clock frequency at the SCL pin | fSCL | 400 | kHz | fCLK ≥ 2MHz | 11 | ||
| Input capacitance (each pin) | CI2C_IN | 10 | pF | Also valid for SPI. | 11 | ||
| Voltage level low (ZACwire) | VOWI_L | 0.2 | VDDA | 11 | |||
| Voltage level high (ZACwire) | VOWI_H | 0.75 | VDDA | 11 |
CAD (KiCad official)
- Symbol:
ZSC31050FAG1-T - Footprint:
Package_SO:SSOP-16_5.3x6.2mm_P0.65mm - 3D model: SSOP-16-208mil (KiCad packages3D, STEP)
- 3D model files:
zsc31050fag1-t-etched.step/zsc31050fag1-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);zsc31050fag1-t.step/zsc31050fag1-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: RENESAS datasheet (30 pp, sha256
214e8cc05d3f5051, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).