ZSC31015EIG1-R from RENESAS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	Bsink	passive	Optional ground connection for the bridge ground, used for power savings.
2	VBP	passive	Positive bridge connection.
3	ExtTemp	passive	External diode connection for external temperature compensation.
4	VBN	passive	Negative bridge connection.
5	Vgate	output	Gate control for external JFET regulation/over-voltage protection.
6	VDD	power_in	Supply voltage, 2.7 to 5.5 V.
7	Sig™	bidirectional	ZACwire™ interface used as analog output, digital output and calibration interface.
8	VSS	power_in	Ground supply.

Key specifications

Parameter	Value
Manufacturer	RENESAS
Package	SOIC-8
Category	Interface ICs
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Analog Supply Voltage	VDD	-0.3		6	V		7
Voltages at Analog I/O - In Pin	VINA	-0.3			V	Max printed as VDD+0.3 V	7
Voltages at Analog I/O - Out Pin	VOUTA	-0.3			V	Max printed as VDD+0.3 V	7
Storage Temperature Range (10 hours)	TSTOR	-50		150	°C	10 hours	7
Storage Temperature Range (<10 hours)	TSTOR <10h	-50		170	°C	<10 hours	7
Analog Supply Voltage to Ground	VDD	2.7	5	5.5	V		7
Analog Supply Voltage (with external JFET Regulator)	VSUPP	5.5	7	30	V	With external JFET regulator	7
Common Mode Voltage	VCM	1			V	Max printed as VDD - 1.3 V	7
Ambient Temperature Range	TAMB	-50		150	C	Maximum EEPROM programming temperature is 85°C	7
External Capacitance between VDD and Ground	CVDD	100	220	470	nF		7
Output Load Resistance to VDD	RL,OUT	5			kΩ	Only needed for Analog Output Mode	7
Output Load Resistance to VSS	RL,OUT	5			kΩ	Only needed for Analog Output Mode	7
Output Load Capacitance	CL,OUT	1	10	15	nF		7
Bridge Resistance	RBR	0.3	100		kΩ		7
Power-On Rise Time	tPON			100	ms		7
Supply Voltage	VDD	2.7	5	5.5	V		8
Supply Current at minimum update rate	IDD		0.25		mA	At minimum update rate	8
Supply Current at maximum update rate	IDD		1	1.4	mA	At maximum update rate	8
Temperature Coefficient - PTAT Source	TCPTAT	20		100	ppm/K		8
Power Supply Rejection Ratio	PSRR	60			dB	Guaranteed by design	8
Power-On Reset Level	POR	1.4		2.6	V		8
Leakage Current Pin VBP,VBN	IIN_LEAK			10	nA	Sensor connection and short check must be disabled	8
Number Write Cycles	nWRI_EEP	100			Cycles	At 150C	8
Data Retention	tWRI_EEP	10			Years	At 100C	8
ADC Resolution	rADC		14		Bit		8
Integral Nonlinearity (INL)	INLADC	-4		4	LSB	Based on ideal slope	8
Differential Nonlinearity (DNL)	DNLADC	-1		1	LSB	Guaranteed by design	8
Max. Output Current	IOUT			2.2	mA	Max. current maintaining accuracy	8
Resolution	Res		12		Bit	Referenced to VDD	8
Absolute Error	EABS	-0.2		0.2	% VDD	DAC input to output	8
Differential Nonlinearity DAC	DNL	-0.9		3	LSB	No missing codes	8
Upper Output Voltage Limit	VOUT		95		% VDD	RL = 5 k	8
Lower Output Voltage Limit	VOUT		16.5		mV	With 5k pull down, 0 to 1V output	8
Output Short Circuit Protection Limit	ISC	3		40	mA	Depends on operating conditions; short circuit protection must be enabled via Diag_cfg	8
Analog Output Noise Peak-to-Peak	VNOISE,PP		5		mV	Shorted input	8
Upper diagnostic output level	VDIA,H		97.5		% VDD		9
Lower diagnostic output level	VDIA,L		2.5		% VDD		9
Minimum load resistor for power loss	RL,OUT_PS	5			kΩ	Pull-up or pull-down in Analog Output Mode	9
External Temperature Signal Input Range	VTSE	150		800	mV		9
Required External Temperature Diode Sensitivity	STTSE	1.9		3.25	mV/K		9
Temperature Span with External Temperature Diode	TTSE_SP	-50		150	°C		9
ZACwire Line Resistance	RZAC,load		3.9		kΩ	Rise time tZAC,rise = 2 R C 5 µs	9
ZACwire Load Capacitance	CZAC,load	0	1	15	nF	Absolute max 15nF	9
Voltage Level Low	VZAC,low	0		0.2	VDD		9
Voltage Level High	VZAC,low	0.8		1	VDD	Printed symbol VZAC,low	9
Start-Up-Time	tSTA			8	ms	Power-up to output, Update_rate = 1 kHz (1 ms)	9
Response Time - Analog Output	tRESP-A	1		2	ms	Update_rate = 1 kHz (1 ms)	9
Response and Transmission Time for Digital Output	tRES, DIG		1.6		ms	Varies with update rate; value given at fastest rate	9
Sampling Rate	fS		1000		Hz	Update_rate = 1 kHz (1 ms)	9
Overall Linearity Error - Digital	ELIND		0.025	0.04	%	Bridge input to output	9
Overall Linearity Error - Analog	ELINA		0.1	0.2	%	Bridge input to output	9
Overall Ratiometricity Error	REout		0.035		%	±10%VDD, not using Bsink feature	9
Overall Accuracy - Digital	ACoutD			0.1	%FSO	-25°C to 85°C, only IC without sensor bridge	10
Overall Accuracy - Analog	ACoutA			0.25	%FSO	-25°C to 85°C, only IC without sensor bridge	10
ZACwire On-chip Pull-up Resistor	RZAC,pu		30		kΩ	On-chip pull-up switched on during Digital Output Mode and CM Mode	25
ZACwire External Pull-up Resistor	RZAC,pu_ext	150			Ω	If master uses no push-pull stage	25
ZACwire Rise Time	tZAC,rise			5	µs	Any user RC network in Sig path must meet this	25
Bsink Transistor rds(on)	rds(on)	8		10	Ω	VDD=5V	6
Minimum Bridge Resistance for Sensor Short Check	RBR	0.3			kΩ	VDD=2.7V	7
Minimum Bridge Resistance for Sensor Short Check	RBR	0.6			kΩ	VDD=5V	7

CAD (KiCad official)

Symbol: ZSC31015EIG1-R
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: zsc31015eig1-r-etched.step / zsc31015eig1-r-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); zsc31015eig1-r.step / zsc31015eig1-r.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: RENESAS datasheet (53 pp, sha256 b5ba673428bd10ce, retrieved 2026-11-08, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

ZSC31015EIG1-R

Verified ZSC31015EIG1-R

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README