component

ZLDO1117QG33TA

Public Made by Adom

by adom

Diodes Incorporated Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-223. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
Name Last commit message Last updated
docs zldo1117qg33ta: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
package.json Publish 0.2.0 · Ray 1mo ago
pads.json page.json: fold the "TAB" entry into pin 2. On SOT-223-3_TabPin2 the tab is not a separate pad - it is that lead - so nothing was ever unconnected, but the page listed it as its own pin and pads.json reported pin-not-in-symbol for a pin that cannot exist. Target chosen because net VOUT matches pin 2; the tab's description is merged into that pin rather than dropped. · Ray 1mo ago
page.json zldo1117qg33ta: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 20h ago
README.md zldo1117qg33ta: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 16d ago
zldo1117qg33ta-etched.fit.json zldo1117qg33ta: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
zldo1117qg33ta-etched.glb zldo1117qg33ta: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
zldo1117qg33ta-etched.step zldo1117qg33ta: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
zldo1117qg33ta.glb Publish 0.1.0 · Ray 1mo ago
zldo1117qg33ta.kicad_mod Publish 0.1.0 · Ray 1mo ago
zldo1117qg33ta.kicad_sym Publish 0.1.0 · Ray 1mo ago
zldo1117qg33ta.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect and oval pad as a SQUARE EAGLE smd; this carries the real pad shape across (0 -> 4 rounded pads) and stops dropping geometry drawn on KiCad User.N layers. Attributes, connects, pads and the pin-1 marker are gated against decreasing and are unchanged. · Ray 1mo ago
zldo1117qg33ta.step Publish 0.1.0 · Ray 1mo ago

ZLDO1117QG33TA

Diodes Incorporated · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-223

ZLDO1117QG33TA from Diodes Incorporated, in a SOT-223. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ADJ/GND power_in Ground pin for the fixed-mode (3.3V) variant ZLDO1117QG33TA. In adjustable variants, a resistor divider from this pin to VOUT sets the output voltage; for the fixed 3.3V version this pin is tied to system ground.
2 VOUT power_out Regulated 3.3V output (2% tolerance, up to 1A). A minimum 4.7uF capacitor (0.05Ω <= ESR <= 0.5Ω) must be connected from this pin to ground to ensure stability. A larger output capacitor is recommended for improved AC load response. Also connected to the exposed tab.
3 VIN power_in Input supply pin (-0.03V to +18V absolute max; 2.7V to 18V recommended). Typically a large storage capacitor (0.05Ω <= ESR <= 0.5Ω) is connected from this pin to ground to keep the input from sagging below the minimum dropout voltage during load transients. VIN must remain at least 1.3V above VOUT (1.5V for correct operation) for the device to regulate properly.
TAB VOUT (Tab) power_out Exposed metal tab electrically connected to VOUT. Used as the primary thermal path; solder to a copper heat-spreading pad on the PCB. Theta_JC = 16 °C/W and Theta_JA = 107 °C/W for SOT-223.

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package SOT-223
Category PMIC
Pins 4

Ordering variants

Same part, different packaging or reel option.

  • ZLDO1117QG33TA
  • ZLDO1117QK33TC

CAD (KiCad official)

  • Symbol: ZLDO1117QG33TA
  • Footprint: Package_TO_SOT_SMD:SOT-223-3_TabPin2
  • 3D model: SOT-223 (KiCad packages3D, STEP)
  • 3D model files: zldo1117qg33ta-etched.step / zldo1117qg33ta-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); zldo1117qg33ta.step / zldo1117qg33ta.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
zldo1117qg33ta.step 64 KB You want the bare part, or you mark your own boards.
zldo1117qg33ta-etched.step 2.1 MB You want the part with ZLDO1117QG33TA already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 525 faces against 75 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (14 pp, sha256 52a05840bdb17cd6, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF