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ZL38063LDF1

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Microchip Tech Audio Interface ICs, QFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232zl38063ldf1factory-2.0.0extractor-text

Verified ZL38063LDF1

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier lcsc, 65 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ZL38063LDF1 · QFN-64-EP(9x9) · 65 pins
  • ✓copper: 65 copper pads, none touching another net
  • ✓datasheet: all 65 pin names found in the 63-page datasheet
  • ✓distributor: lcsc C2662582, digikey 150-ZL38063LDF1TR-ND, mouser 494-ZL38063LDF1
  • ✓family: QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-xhi0j1qj/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): the datasheet dimensions give no height or body size to compare (datasheet p.59)
  • ✓pads: 65 pins = 65 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 65 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ zl38063ldf1.kicad_sym✓ zl38063ldf1.kicad_mod✓ zl38063ldf1.step
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ZL38063LDF1

Microchip Tech · Audio Interface ICs · QFN-64-EP(9x9)

ZL38063LDF1 from Microchip Tech, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SM_CLK tri_state Master SPI port clock output (tristate) with a maximum frequency of 8 MHz as stated in the pin description.
2 SM_MISO input Master SPI port data input that receives data from the external Flash device.
3 SM_MOSI tri_state Master SPI port data output (tristate) to the external Flash device.
4 DVDD12 power_in Core +1.2 V supply; connect to a +1.2 V ±5% supply with a 100 nF, 20%, 10 V ceramic capacitor on each pin decoupled to VSS.
5 DVDD33 power_in Digital +3.3 V supply; connect to a +3.3 V ±5% supply with a 100 nF, 20%, 10 V ceramic capacitor on each pin decoupled to VSS.
6 DAC1_M output DAC 1 minus differential amplifier output; pin functionality is firmware dependent.
7 DAC1_P output DAC 1 plus differential amplifier output; pin functionality is firmware dependent.
8 DAC2_P output DAC 2 plus differential amplifier output; pin functionality is firmware dependent.
9 DAC2_M output DAC 2 minus differential amplifier output; pin functionality is firmware dependent.
10 AVDD33 power_in Analog +3.3 V supply; connect to a +3.3 V ±5% supply with 100 nF decoupling to VSS on each pin.
11 AVDD33 power_in Analog +3.3 V supply; connect to a +3.3 V ±5% supply with 100 nF decoupling to VSS on each pin.
12 CDAC output DAC reference output that requires capacitive decoupling (0.1 µF to VSS per the DAC bias circuit section).
13 CREF output Common mode reference output that requires 0.1 µF and 1.0 µF ceramic decoupling to VSS.
14 DVDD12 power_in Core +1.2 V supply; connect to a +1.2 V ±5% supply with 100 nF decoupling to VSS on each pin.
15 RESET input Active-low reset: low for 100 ns to 1 µs gives a digital reset and low for more than 10 µs gives an analog reset; a 10 kΩ pull-up to DVDD33 is required if not continuously driven.
16 VDD12_CTRL output Analog control for the external FET when EXT_SEL is tied to VSS, or a CMOS output to shut down an external LDO when EXT_SEL is tied to DVDD33.
17 EXT_SEL input Selects the +1.2 V source: tie to DVDD33 for an externally supplied +1.2 V, or tie to VSS for the internally generated +1.2 V.
18 DMIC_CLK output Clock output for digital microphones and digital electret microphone pre-amplifier devices.
19 DMIC_IN1 input Digital microphone input 1 for a stereo or mono digital microphone; tie to VSS if unused.
20 DMIC_IN2 input Digital microphone input 2 for a stereo or mono digital microphone; tie to VSS if unused.
21 DVDD33 power_in Digital +3.3 V supply; connect to a +3.3 V ±5% supply with 100 nF decoupling to VSS on each pin.
22 XI input Crystal oscillator input for the 12.000 MHz crystal or clock oscillator that drives the internal PLL.
23 XO output Crystal oscillator output for the 12.000 MHz crystal that drives the internal PLL.
24 DVDD12 power_in Core +1.2 V supply; connect to a +1.2 V ±5% supply with 100 nF decoupling to VSS on each pin.
25 NC unconnected No connection; leave unconnected and do not use as a tie point.
26 NC unconnected No connection; leave unconnected and do not use as a tie point.
27 NC unconnected No connection; leave unconnected and do not use as a tie point.
28 DVDD33_XTAL power_in Crystal digital supply that must be connected to a +3.3 V source capable of delivering 10 mA.
29 PCLKA/I2S_SCKA bidirectional PCM port A clock equal to the DRA/DXA bit rate (output in TDM master mode, input in slave mode) or I2S port A serial clock; a 100 kΩ pull-down to VSS is required and the pin must be tied to VSS if unused.
30 FSA/I2S_WSA bidirectional PCM port A frame sync (input in slave mode, frame pulse output in master mode) or I2S port A word select; tie to VSS if unused.
31 DRA/I2S_SDIA input PCM port A serial data input operating at PCLK data rates or I2S port A serial data input; tie to VSS if unused.
32 DXA/I2S_SDOA output PCM port A serial data output operating at PCLK data rates or I2S port A serial data output.
33 GPIO_0 bidirectional General-purpose I/O for low-frequency signaling with internal pull-down on input; it must be pulled low or left floating when coming out of reset.
34 GPIO_1 bidirectional General-purpose I/O for low-frequency signaling with internal pull-down on input; it must be pulled low or left floating when coming out of reset.
35 DVDD33 power_in Digital +3.3 V supply; connect to a +3.3 V ±5% supply with 100 nF decoupling to VSS on each pin.
36 GPIO_2 bidirectional General-purpose I/O for low-frequency signaling with internal pull-down on input; it also provides bootstrap functionality per the bootstrap modes table.
37 GPIO_3 bidirectional General-purpose I/O for low-frequency signaling with internal pull-down on input; it requires a pull-up resistor on the master device when two ZL38063 devices are chained.
38 GPIO_4 bidirectional General-purpose I/O for low-frequency signaling with internal pull-down on input; it requires a pull-up resistor on the slave device to identify master and slave in two-device operation.
39 GPIO_5 bidirectional General-purpose I/O for low-frequency signaling with internal pull-down on input.
40 GPIO_6 bidirectional General-purpose I/O for low-frequency signaling with internal pull-down on input.
41 GPIO_7 bidirectional General-purpose I/O for low-frequency signaling with internal pull-down on input.
42 DVDD12 power_in Core +1.2 V supply; connect to a +1.2 V ±5% supply with 100 nF decoupling to VSS on each pin.
43 GPIO_8 bidirectional General-purpose I/O for low-frequency signaling with internal pull-down on input.
44 GPIO_10 bidirectional General-purpose I/O for low-frequency signaling with internal pull-down on input.
45 GPIO_11 bidirectional General-purpose I/O for low-frequency signaling with internal pull-down on input.
46 DVDD33 power_in Digital +3.3 V supply; connect to a +3.3 V ±5% supply with 100 nF decoupling to VSS on each pin.
47 GPIO_12 bidirectional General-purpose I/O for low-frequency signaling with internal pull-down on input; not available on the WLCSP package.
48 GPIO_13 bidirectional General-purpose I/O for low-frequency signaling with internal pull-down on input; not available on the WLCSP package.
49 UART_TX tri_state UART transmit serial data output (tristate) at a fixed 115.2K baud, 8 data bits, 1 stop bit and no parity, used for debug and tuning.
50 UART_RX input UART receive serial data input at a fixed 115.2K baud, 8 data bits, 1 stop bit and no parity, used for debug and tuning.
51 DVDD33 power_in Digital +3.3 V supply; connect to a +3.3 V ±5% supply with 100 nF decoupling to VSS on each pin.
52 HCLK input HBI SPI slave port clock input with a maximum frequency of 25 MHz; tie to VSS in I2C mode or if unused.
53 HCS input HBI SPI slave active-low chip select; it doubles as the I2C serial clock input (pull-up required) in I2C mode, and must be tied to VSS if unused.
54 VSS power_in Ground; connect to the digital ground plane.
55 HDIN input HBI SPI slave port data input that also selects the slave address in I2C mode; tie to VSS if unused.
56 HDOUT bidirectional HBI SPI slave port data output (tristate) that serves as I2C SDA (pull-up required) in I2C mode.
57 HINT output HBI interrupt output that the host can configure as either CMOS or open drain.
58 DVDD12 power_in Core +1.2 V supply; connect to a +1.2 V ±5% supply with 100 nF decoupling to VSS on each pin.
59 DVDD33 power_in Digital +3.3 V supply; connect to a +3.3 V ±5% supply with 100 nF decoupling to VSS on each pin.
60 PCLKB/I2S_SCKB bidirectional PCM port B clock equal to the DRB/DXB bit rate (output in TDM master mode, input in slave mode) or I2S port B serial clock; tie to VSS if unused.
61 FSB/I2S_WSB bidirectional PCM port B frame sync (input in slave mode, frame pulse output in master mode) or I2S port B word select; tie to VSS if unused.
62 DRB/I2S_SDIB input PCM port B serial data input operating at PCLK data rates or I2S port B serial data input; tie to VSS if unused.
63 DXB/I2S_SDOB output PCM port B serial data output operating at PCLK data rates or I2S port B serial data output.
64 GPIO_9/SM_CS bidirectional Master SPI port chip select output (input internal pull-up, tristate output) shared with GPIO_9, with internal pull-down on input when used as GPIO.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-64-EP(9x9)
Category Communication Interface Chip/UART/485/232
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (DVDD33, AVDD33) -0.5 4 V 40
Core supply voltage (DVDD12) -0.5 1.32 V 40
Input voltage -0.5 4 V 40
Continuous current at digital outputs 15 mA 40
Reflow temperature 260 °C 10 sec., MSL3, per JEDEC J-STD-020 40
Storage temperature -55 125 °C 40
Ambient temperature TA -40 85 °C 40
Analog supply voltage VAVDD33 3.135 3.3 3.465 V 41
Core supply voltage VDVDD12 1.14 1.2 1.26 V 41
Crystal I/O voltage VXI 2.5 2.625 V 41
Weak pull-up current IPU 38 63 101 µA Input at 0 V 43
Weak pull-down current IPD 19 41 158 µA Input at +3.3 V 43
Output high voltage VOH 2.4 V At 12 mA 43
Output low voltage VOL 0.4 V At 12 mA 43
Input leakage (input pins) IIL 5 µA 0 to +3.3 V 43
Input leakage (bi-directional pins) IBL 5 µA 0 to +3.3 V 43
Output high impedance leakage IOZ 5 µA 0 to +3.3 V 43
Output rise time tRT 1.25 ns 10% to 90%, CLOAD = 20 pF 43
Output fall time tFT 1.25 ns 90% to 10%, CLOAD = 20 pF 43
Frequency response (sample rate 48 kS/s) fR 20 20000 Hz Sample rate = 48 kS/s; 3 dB cutoff includes external AC coupling 44
Allowable capacitive load to ground CL 100 pF At each DAC output 44
External clocking frequency accuracy AOSC -50 50 ppm Not tested in production 46
External clocking duty cycle DCOSC 40 60 % 46
PCLK period tPCY 122 7812.5 ns PCLK frequency must be within 100 ppm 48
FS delay (output rising or falling) tFSD 2 15 ns CLOAD = 40 pF 48
FS delay (output rising or falling) tFSD 2 25 ns CLOAD = 150 pF 48
Data output delay tDOD 2 15 ns CLOAD = 40 pF 48
Data output delay tDOD 2 25 ns CLOAD = 150 pF 48
Data output delay to High-Z tDOZ 0 10 ns Guaranteed by design, not tested in production 48
Allowed baud rate deviation (8 bits, no parity) 4.86 % Guaranteed by design, not tested in production 55
SM_CLK clock period tMSCP 40 320 ns Max. 25.0 MHz 56
SM_CLK driving edge to SM_MOSI valid tMSOD -1 2 ns CLOAD = 40 pF 56
SCLK clock frequency (I2C slave) fSCL 0 400 kHz 54
I2S_SCK falling edge to I2S_SDO valid (slave) tISOD 2 15 ns CLOAD = 40 pF 51
I2S_SCK falling edge to I2S_WS (master) tIMOD 2 15 ns CLOAD = 40 pF 52
I2S_SCK falling edge to I2S_SDO valid (master) tIMOD 2 15 ns CLOAD = 40 pF 52

CAD (KiCad official)

  • Symbol: ZL38063LDF1
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: zl38063ldf1-etched.step / zl38063ldf1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); zl38063ldf1.step / zl38063ldf1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (63 pp, sha256 be635cd1b193fc47, retrieved 2026-10-30, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF