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ZJC2541-14BSABR
Public Made by Adomby adom
ZJW Digital To Analog Converters (DACs), SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownZJC2541-14BSABR
ZJW · Digital To Analog Converters (DACs) · SOIC-8
ZJC2541-14BSABR from ZJW, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | output | DAC voltage output (unbuffered), range 0 V to VREF. |
| 2 | AGND | power_in | Analog ground. |
| 3 | REF | input | Voltage reference input, range 2 V to VDD, code-dependent input impedance so drive from a low impedance source. |
| 4 | CS | input | Serial digital chip select input, active low. |
| 5 | SCLK | input | Serial data clock input, up to 50 MHz. |
| 6 | DIN | input | Serial digital data input. |
| 7 | DGND | power_in | Digital ground. |
| 8 | VDD | power_in | Supply voltage input, 2.7 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ZJW |
| Package | SOIC-8 |
| Category | ADC/DAC/Data Conversion |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Resolution | 14 | bits | ZJC2541/3-14 | 9 | |||
| Integral Nonlinear Error | INL | -0.5 | 0.2 | 0.5 | LSB | 14 bits, full temperature range (typ printed ± 0.2) | 9 |
| Differential Nonlinear Error | DNL | -0.25 | 0.1 | 0.25 | LSB | 14 bits, full temperature range (typ printed ± 0.1) | 9 |
| Gain Error | GE | -0.3 | 0.1 | 0.3 | LSB | 14 bits, TA = 25 °C (typ printed ± 0.1) | 9 |
| Gain Error | GE | -0.5 | 0.15 | 0.5 | LSB | 14 bits, -40 °C ≤ TA ≤ 85 °C (typ printed ± 0.15) | 9 |
| Gain Error | GE | -0.75 | 0.25 | 0.75 | LSB | 14 bits, -40 °C ≤ TA ≤ 125 °C (typ printed ± 0.25) | 9 |
| Zero Code Error | ZCE | -0.5 | 0.15 | 0.5 | LSB | 14 bits, full temperature range (typ printed ± 0.15) | 9 |
| Gain Error Temperature Drift | 0.05 | ppm/°C | printed ± 0.05 | 9 | |||
| Zero Code Error Temperature Coefficient | 0.1 | ppm/°C | printed ± 0.1 | 9 | |||
| Output Voltage Range | 0 | V | upper limit printed as VREF - 1 LSB | 9 | |||
| Output Voltage Settling Time | 1 | μs | 14 bits, to 1/2 LSB of full scale, CL = 10 pF | 10 | |||
| Slew rate | 16 | V/μs | CL = 10 pF measured from 0 % to 63 % | 10 | |||
| DAC Output Impedance | 6.25 | kΩ | General tolerance 20 % | 10 | |||
| Output Noise Density | 11 | nV/√Hz | Frequency = 1 kHz | 10 | |||
| Reference Voltage Range | 2 | V | upper limit VDD | 10 | |||
| Reference Input Resistance | 8 | kΩ | varies with code | 10 | |||
| Input High Voltage | VIH | 2.4 | V | printed 2.4/0.9*VLOGIC | 10 | ||
| Input Low Voltage | VIL | 0.8 | V | printed 0.8/0.1*VLOGIC | 10 | ||
| Input Current | -1 | 1 | µA | 10 | |||
| Power Supply | VDD | 2.7 | 5.5 | V | 10 | ||
| Electric Current | IVDD | 120 | µA | VDD = 5 V | 10 | ||
| Digital Interface Power | VLOGIC | 1.8 | 5.5 | V | 10 | ||
| Rated Performance Temperature Range | TMIN to TMAX | -40 | 125 | °C | 10 | ||
| SCLK Frequency | fSCLK | 50 | MHz | 2.7 V ≤ VLOGIC ≤ 5.5 V | 11 | ||
| SCLK Period | t1 | 20 | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 11 | ||
| SCLK High Level Time | t2 | 9 | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 11 | ||
| SCLK Low Level Time | t3 | 9 | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 11 | ||
| CS Low To SCLK High Setup Time | t4 | 5 | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 11 | ||
| CS High To SCLK High Setup Time | t5 | 50 | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 11 | ||
| SCLK High To CS Low Hold Time | t6 | 5 | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 11 | ||
| SCLK High To CS High Hold Time | t7 | 5 | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 11 | ||
| Data Creation Time | t8 | 10 | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 11 | ||
| Data Hold Time | t9 | 5 | ns | VINH = 90 % of VDD, VINL = 10 % of VDD; 2.7 V ≤ VLOGIC ≤ 5.5 V | 11 | ||
| CS High Time Between Low Levels | t10 | 15 | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 11 | ||
| VDD to AGND | VDD | -0.3 | 6 | V | 8 | ||
| REF to AGND | REF | -0.3 | 6 | V | upper limit printed as VDD + 0.3 V | 8 | |
| Digital Input to DGND | -0.3 | 6 | V | upper limit printed as VDD + 0.3 V | 8 | ||
| Input current to pins except VDD | -10 | 10 | mA | 8 | |||
| Storage Temperature Range | -65 | 150 | °C | 8 | |||
| Junction Temperature | 150 | °C | 8 | ||||
| Lead Temperature | 300 | °C | Soldering, 10 seconds | 8 | |||
| Maximum Reflow Temperature | 260 | °C | IPC/JEDEC J-STD-020 compliant | 8 | |||
| ESD Human Body Model | HBM | 3.5 | kV | 8 | |||
| ESD Charged Device Model | CDM | 2 | kV | 8 | |||
| Thermal Resistance Junction-to-Ambient | θJA | 122.3 | °C/W | SOIC-8 | 8 | ||
| Thermal Resistance Junction-to-Case | θJC | 60.4 | °C/W | SOIC-8 | 8 |
CAD (KiCad official)
- Symbol:
ZJC2541-14BSABR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
zjc2541-14bsabr-etched.step/zjc2541-14bsabr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);zjc2541-14bsabr.step/zjc2541-14bsabr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ZJW datasheet (27 pp, sha256
fe157297de4ff8e6, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).