# ZH639D0JT

**Semiment** · Gate Drivers · TSSOP-20

ZH639D0JT from Semiment, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | HIN1 | input | High-side logic input for channel 1, with logic input levels compatible with 3.3V/5V and an absolute maximum of 6 V (-0.3 V to 6 V). |
| 2 | HIN2 | input | High-side logic input for channel 2, with logic input levels compatible with 3.3V/5V and an absolute maximum of 6 V (-0.3 V to 6 V). |
| 3 | HIN3 | input | High-side logic input for channel 3, with logic input levels compatible with 3.3V/5V and an absolute maximum of 6 V (-0.3 V to 6 V). |
| 4 | LIN1 | input | Low-side logic input for channel 1, with logic input levels compatible with 3.3V/5V and an absolute maximum of 6 V (-0.3 V to 6 V). |
| 5 | LIN2 | input | Low-side logic input for channel 2, with logic input levels compatible with 3.3V/5V and an absolute maximum of 6 V (-0.3 V to 6 V). |
| 6 | LIN3 | input | Low-side logic input for channel 3, with logic input levels compatible with 3.3V/5V and an absolute maximum of 6 V (-0.3 V to 6 V). |
| 7 | VCC | power_in | Chip supply input, recommended 5 V to 12 V, with an absolute maximum range of -0.3 V to 20 V. |
| 8 | COM(LSS) | power_in | Chip ground; for the 20-pin version the datasheet recommends connecting COM preferably to the power ground. |
| 9 | LO3 | output | Low-side gate drive output for channel 3, limited to -0.3 V to VCC + 0.3 V. |
| 10 | LO2 | output | Low-side gate drive output for channel 2, limited to -0.3 V to VCC + 0.3 V. |
| 11 | LO1 | output | Low-side gate drive output for channel 1, limited to -0.3 V to VCC + 0.3 V. |
| 12 | HS3 | output | High-side floating ground (switch node) for channel 3, with an absolute range of -5 V to 100 V. |
| 13 | HO3 | output | High-side gate drive output for channel 3, referenced to HS3 and limited to HS - 0.3 V to HB + 0.3 V. |
| 14 | HB3 | power_in | High-side floating bootstrap supply for channel 3, rated up to 120 V absolute maximum, with HB-HS limited to 20 V. |
| 15 | HS2 | output | High-side floating ground (switch node) for channel 2, with an absolute range of -5 V to 100 V. |
| 16 | HO2 | output | High-side gate drive output for channel 2, referenced to HS2 and limited to HS - 0.3 V to HB + 0.3 V. |
| 17 | HB2 | power_in | High-side floating bootstrap supply for channel 2, rated up to 120 V absolute maximum, with HB-HS limited to 20 V. |
| 18 | HS1 | output | High-side floating ground (switch node) for channel 1, with an absolute range of -5 V to 100 V. |
| 19 | HO1 | output | High-side gate drive output for channel 1, referenced to HS1 and limited to HS - 0.3 V to HB + 0.3 V. |
| 20 | HB1 | power_in | High-side floating bootstrap supply for channel 1, rated up to 120 V absolute maximum, with HB-HS limited to 20 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Semiment |
| Package | TSSOP-20 |
| Category | Motor Driver ICs |
| Pins | 20 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High-Side Floating Supply Voltage (HBx) | HBx | -0.3 |  | 120 | V |  | 5 |
| High-Side Floating Ground Voltage (HSx) | HSx | -5 |  | 100 | V |  | 5 |
| HBx-HSx Floating Supply Voltage | HBx-HSx | -10 |  | 110 | V | 1us | 5 |
| HBx-HSx Floating Supply Voltage | HBx-HSx | -0.3 |  | 20 | V |  | 5 |
| High-Side Output, HS | HOx | -0.3 |  |  | V |  | 5 |
| Low-Side Output, LS | LOx | -0.3 |  |  | V |  | 5 |
| VCC Supply Voltage | VCC | -0.3 |  | 20 | V |  | 5 |
| High-Side Logic Input Voltage | HINx | -0.3 |  | 6 | V |  | 5 |
| Low-Side Logic Input Voltage | LINx | -0.3 |  | 6 | V |  | 5 |
| Ambient Temperature | TA | -40 |  | 125 | °C |  | 5 |
| Storage Temperature | Tstg | -55 |  | 150 | °C |  | 5 |
| High-Side Floating Ground Voltage | VHSx | -5 |  | 100 | V |  | 5 |
| Supply Voltage | VCC | 5 |  | 12 | V |  | 5 |
| Low-Side Output Voltage | VLOx | 0 |  |  | V |  | 5 |
| Logic Input Voltage (HINx & LINx) | VINx | 0 |  | 5 | V |  | 5 |
| Ambient Temperature | TA | -40 |  | 125 | °C |  | 6 |
| VCC Quiescent Current | IQ-VCC |  | 50 | 200 | μA | HINx = LINx = 0, VSx=0 | 7 |
| Dynamic Operating Current | IOP |  | 1.8 | 2.9 | mA | Complementary 25k, 50%, PWM, No Load | 7 |
| HO Output Strong Pull-Down Resistance | RHPD |  | 0.8 | 1 | Ω | HOx=HSx+100mV, HINx=0 | 8 |
| LO Output Strong Pull-Down Resistance | RLPD |  | 0.8 | 1 | Ω | LOx=100mV, LINx=0 | 8 |
| Turn-On Propagation Delay Time | tPDLH |  | 100 | 250 | ns |  | 8 |
| Turn-Off Propagation Delay Time | tPDHL |  | 100 | 250 | ns |  | 8 |
| Output Rise Time | tRISE |  | 100 | 170 | ns | 10% ~ 90%, CL = 1nF | 8 |
| Output Fall Time | tFALL |  | 50 | 90 | ns | 10% ~ 90%, CL = 1nF | 8 |
| Dead Time | DT | 50 | 100 | 150 | ns | CL = 1nF | 8 |
| HBx Rising Threshold | VVHBR |  | 3.8 |  | V | VHBRx = VHBx, VHSx | 7 |
| HBx Falling Threshold | VVHBF |  | 2.2 |  | V |  | 7 |
| HBx Threshold Hysteresis | VVHBH |  | 1.6 |  | V |  | 7 |
| Bootstrap Supply Leakage Current | IBL |  | 50 |  | μA | HBx = HSx = 100 V | 7 |
| Bootstrap Supply Leakage Current (150℃) | IBL |  | 150 |  | uA | 150℃ | 7 |
| High-Level Input Threshold Voltage | VIH |  | 2.2 |  | V |  | 7 |
| Low-Level Input Threshold Voltage | VIL |  | 0.7 |  | V |  | 7 |
| Input Pin Threshold Voltage Hysteresis | VIN-Hys |  | 0.7 |  | V |  | 7 |
| Input Pin Pull-Down Resistance | RIN |  | 200 |  | kΩ |  | 7 |
| High-Side Pull-Up Current | IHPU |  | 170 |  | mA | HOx = HSx, HINx=1 | 7 |
| High-Side Pull-Down Current | IHPD |  | 150 |  | mA | HOx = HBx, HINx=0 | 7 |
| High-Side Strong Pull-Down Current | IHPDST |  | 2.5 |  | A | HINx=0, HOx=HSx+5V | 7 |
| Low-Side Pull-Up Current | ILPU |  | 140 |  | mA | LOx=0, LINx=1 | 7 |
| Low-Side Pull-Down Current | ILPD |  | 150 |  | mA | LOx=VCC, LINx=0 | 7 |
| Low-Side Strong Pull-Down Current | IHPDST |  | 2.5 |  | A | LINx=0, LOx=LSS+5V | 7 |
| Low-to-High Propagation Delay Matching | tPDRM |  | 60 |  | ns |  | 8 |
| High-to-Low Propagation Delay Matching | tPDFM |  | 60 |  | ns |  | 8 |

## CAD (KiCad official)

- Symbol: `ZH639D0JT`
- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`
- 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files: `zh639d0jt-etched.step` / `zh639d0jt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `zh639d0jt.step` / `zh639d0jt.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Semiment datasheet](docs/zh639d0jt-datasheet.pdf) (19 pp, sha256 `ecbf32266cf81b1d`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/zh639d0jt-datasheet.pdf)