component

ZGAD65D14C

Public Made by Adom

by adom

Zynalog Analog To Digital Converters (ADCs), QFN-64(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionzgad65d14cfactory-2.0.0extractor-text

Verified ZGAD65D14C

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier lcsc, 65 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ZGAD65D14C · QFN-64(9x9) · 65 pins
  • ✓copper: 65 copper pads, none touching another net
  • ✓datasheet: all 65 pin names found in the 18-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-c1l9p0f3/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.17)
  • ✓pads: 65 pins = 65 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 65 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ zgad65d14c.kicad_sym✓ zgad65d14c.kicad_mod✓ zgad65d14c.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
zgad65d14c / README.md
History Download
Ray Publish 0.1.0 0294f01 6d ago

ZGAD65D14C

Zynalog · Analog To Digital Converters (ADCs) · QFN-64(9x9)

ZGAD65D14C from Zynalog, in a QFN-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in 1.8V analog supply, bypass to ground with 0.1µF ceramic capacitor (pins 1, 2, 64 may share one capacitor).
2 VDD power_in 1.8V analog supply, bypass to ground with 0.1µF ceramic capacitor (pins 1, 2, 64 may share one capacitor).
3 GND power_in Power ground; the exposed pad on the back must be soldered to PCB ground.
4 VinA+ input Channel A differential analog input, positive.
5 VinA- input Channel A differential analog input, negative.
6 GND power_in Power ground; the exposed pad on the back must be soldered to PCB ground.
7 SENSE input Reference select: tie to VDD for internal reference with ±1V input range, or apply an external 1.2V to 1.3V reference for an input range of ±0.8*VSENSE.
8 VREF power_in Reference voltage output, nominally 1.25V, bypass to ground with 2.2µF ceramic capacitor.
9 GND power_in Power ground; the exposed pad on the back must be soldered to PCB ground.
10 VCM output Common-mode bias output, nominally 0.435*VDD, used to set the analog input common mode, bypass to ground with 0.1µF ceramic capacitor.
11 GND power_in Power ground; the exposed pad on the back must be soldered to PCB ground.
12 VinB- input Channel B differential analog input, negative.
13 VinB+ input Channel B differential analog input, positive.
14 GND power_in Power ground; the exposed pad on the back must be soldered to PCB ground.
15 VDD power_in 1.8V analog supply, bypass to ground with 0.1µF ceramic capacitor (pins 15, 16, 17 may share one capacitor).
16 VDD power_in 1.8V analog supply, bypass to ground with 0.1µF ceramic capacitor (pins 15, 16, 17 may share one capacitor).
17 VDD power_in 1.8V analog supply, bypass to ground with 0.1µF ceramic capacitor (pins 15, 16, 17 may share one capacitor).
18 GND power_in Power ground; the exposed pad on the back must be soldered to PCB ground.
19 CLK+ input Clock input; conversion starts on the rising edge.
20 CLK- input Clock input; conversion starts on the falling edge.
21 GND power_in Power ground; the exposed pad on the back must be soldered to PCB ground.
22 OFB output Overflow/underflow digital CMOS output; high when overflow or underflow occurs (OF is low).
23 OF output Overflow/underflow digital CMOS output; low when overflow or underflow occurs (OFB is high).
24 DB0 output Channel B CMOS digital output bit 0 (D13 is the MSB).
25 DB1 output Channel B CMOS digital output bit 1 (D13 is the MSB).
26 DB2 output Channel B CMOS digital output bit 2 (D13 is the MSB).
27 DB3 output Channel B CMOS digital output bit 3 (D13 is the MSB).
28 DB4 output Channel B CMOS digital output bit 4 (D13 is the MSB).
29 DB5 output Channel B CMOS digital output bit 5 (D13 is the MSB).
30 DB6 output Channel B CMOS digital output bit 6 (D13 is the MSB).
31 DB7 output Channel B CMOS digital output bit 7 (D13 is the MSB).
32 DVDD power_in 1.8V supply for the digital output drivers, bypass to ground with its own 0.1µF ceramic capacitor.
33 DGND power_in Ground for the digital output drivers.
34 DB8 output Channel B CMOS digital output bit 8 (D13 is the MSB).
35 DB9 output Channel B CMOS digital output bit 9 (D13 is the MSB).
36 DB10 output Channel B CMOS digital output bit 10 (D13 is the MSB).
37 DB11 output Channel B CMOS digital output bit 11 (D13 is the MSB).
38 DB12 output Channel B CMOS digital output bit 12 (D13 is the MSB).
39 DB13 output Channel B CMOS digital output bit 13, the MSB.
40 CLKOUTB output CMOS data output clock, inverted relative to CLKOUT.
41 CLKOUT output CMOS data output clock.
42 DA0 output Channel A CMOS digital output bit 0 (D13 is the MSB).
43 DA1 output Channel A CMOS digital output bit 1 (D13 is the MSB).
44 DA2 output Channel A CMOS digital output bit 2 (D13 is the MSB).
45 DA3 output Channel A CMOS digital output bit 3 (D13 is the MSB).
46 DA4 output Channel A CMOS digital output bit 4 (D13 is the MSB).
47 DA5 output Channel A CMOS digital output bit 5 (D13 is the MSB).
48 DGND power_in Ground for the digital output drivers.
49 DVDD power_in 1.8V supply for the digital output drivers, bypass to ground with its own 0.1µF ceramic capacitor.
50 DA6 output Channel A CMOS digital output bit 6 (D13 is the MSB).
51 DA7 output Channel A CMOS digital output bit 7 (D13 is the MSB).
52 DA8 output Channel A CMOS digital output bit 8 (D13 is the MSB).
53 DA9 output Channel A CMOS digital output bit 9 (D13 is the MSB).
54 DA10 output Channel A CMOS digital output bit 10 (D13 is the MSB).
55 DA11 output Channel A CMOS digital output bit 11 (D13 is the MSB).
56 DA12 output Channel A CMOS digital output bit 12 (D13 is the MSB).
57 DA13 output Channel A CMOS digital output bit 13, the MSB.
58 GND power_in Power ground; the exposed pad on the back must be soldered to PCB ground.
59 SPI_MISO output SPI MISO in serial mode (MODE=0); open-drain output needing a 2K pull-up to the 1.8V to 3.3V SPI supply for readback, no function in parallel mode.
60 SPI_MOSI input SPI MOSI port in serial interface mode (MODE=0).
61 SPI_SCLK input SPI SCLK in serial mode (MODE=0); in parallel mode (MODE=VDD) low is normal operation and high (1.8V to 3.3V) enters sleep mode.
62 SPI_CS input SPI CS in serial mode (MODE=0); in parallel mode (MODE=VDD) low turns the clock duty cycle stabilizer off and high (1.8V to 3.3V) turns it on.
63 MODE input Serial/parallel mode select: GND enables SPI mode, VDD enables parallel GPIO mode; connect directly to GND or VDD, not to a logic signal.
64 VDD power_in 1.8V analog supply, bypass to ground with 0.1µF ceramic capacitor (pins 1, 2, 64 may share one capacitor).
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Zynalog
Package QFN-64(9x9)
Category ADC/DAC/Data Conversion
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Analog supply voltage VDD 1.7 1.8 1.9 V 4
Digital supply voltage DVDD 1.7 1.8 1.9 V 4
Analog supply current I_VDD 162 165 mA 4
Digital supply current I_DVDD 12 mA 4
Power at max sample rate Power 315 mW 4
Low power mode P_lowpower 136 mW 4
Sleep mode P_sleep 0.65 mW 4
Integral nonlinearity INL -2 1 2 LSB 4
Differential nonlinearity DNL -0.6 0.35 0.6 LSB 4
Offset error Offset Error -13 5 13 mV 4
Gain error Gain Error -4 1 2.2 %FS 4
Signal-to-noise ratio SNR 71 dB 4
Spurious-free dynamic range SFDR 92 dB 4
Clock input to data acquisition delay tAP 0.2 ns VDD=1.8V, DVDD=1.8V, fS=65MHz 9
Clock high time tH 7.6 8 ns VDD=1.8V, DVDD=1.8V, fS=65MHz 9
Clock low time tL 7.6 8 ns VDD=1.8V, DVDD=1.8V, fS=65MHz 9
Clock input to clock output delay tC 1.3 1.6 2 ns VDD=1.8V, DVDD=1.8V, fS=65MHz 9
Clock input to data output delay tD 1.7 2 2.3 ns VDD=1.8V, DVDD=1.8V, fS=65MHz 9
Clock output to data output skew tSKEW 0.3 0.4 0.55 ns tC - tD; VDD=1.8V, DVDD=1.8V, fS=65MHz 9
CS low to CLK setup time tS 5 ns SPI_MISO pull-up 2KΩ 14
Data setup time tDS 5 ns SPI_MISO pull-up 2KΩ 14
Data hold time tDH 5 ns SPI_MISO pull-up 2KΩ 14
CLK to data output delay tDO 125 ns SPI_MISO pull-up 2KΩ 14
Clock period (write) tSCK 40 ns SPI_MISO pull-up 2KΩ 14
Clock period (readback) tSCK 250 ns SPI_MISO pull-up 2KΩ 14
CLK to CS high hold time tH 5 ns SPI_MISO pull-up 2KΩ 14
Supply voltage VDD,DVDD -0.3 2 V 6
Analog input voltage Analog Vin -0.3 V -0.3 to VDD+0.2 6
CLK, SENSE input voltage CLK,SENSE -0.3 V -0.3 to VDD+0.2 6
SPI/GPIO digital voltage SPI 3.9 V VDD to 3.9 6
CMOS data output voltage Data Output -0.3 V -0.3 to DVDD+0.2 6
Working temperature WORKING TEMP -40 85 °C 6
Storage temperature STORAGE TEMP -65 150 °C 6

CAD (KiCad official)

  • Symbol: ZGAD65D14C
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: QFN-64(9x9) (KiCad packages3D, STEP)
  • 3D model files: zgad65d14c-etched.step / zgad65d14c-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); zgad65d14c.step / zgad65d14c.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Zynalog datasheet (18 pp, sha256 6ea7fa4f9e9c9972, retrieved 2026-10-31, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF