ZGAD250S12

{
  "slug": "zgad250s12",
  "version": "0.1.0",
  "type": "component",
  "description": "Zynalog Analog To Digital Converters (ADCs), QFN-40(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "adc-dac-data conversion",
    "zgad250s12",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "zgad250s12.kicad_sym",
    "zgad250s12.kicad_mod",
    "zgad250s12.glb",
    "zgad250s12.step",
    "zgad250s12.lbr",
    "docs/hero.png",
    "docs/zgad250s12-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "zgad250s12-hero.glb",
    "zgad250s12-hero.overlay.json",
    "zgad250s12-etched.glb"
  ],
  "component": {
    "mpn": "ZGAD250S12",
    "manufacturer": "Zynalog",
    "package": "QFN-40(6x6)",
    "pin_count": 41,
    "category": "ADC/DAC/Data Conversion",
    "subcategory": "Analog To Digital Converters (ADCs)",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/fa73fdff2dfb7a384e2b258cf574a00c.pdf",
    "parts": {
      "symbol": "zgad250s12.kicad_sym",
      "footprint": "zgad250s12.kicad_mod",
      "model_3d": "zgad250s12-hero.glb",
      "model_3d_plain": "zgad250s12-etched.glb",
      "model_3d_step": "zgad250s12-etched.step",
      "model_3d_step_plain": "zgad250s12.step",
      "lbr": "zgad250s12.lbr"
    },
    "distributor_links": {
      "lcsc": "C20416585"
    },
    "distributor_check": {
      "checked_at": "2026-10-30T16:44:41Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "no match"
      },
      "mouser": {
        "pn": null,
        "status": "no match"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VDD",
        "type": "power_in",
        "description": "1.8V analog supply, bypassed to ground with a 0.1µF ceramic capacitor (pins 1 and 2 may share one capacitor)."
      },
      {
        "number": "2",
        "name": "VDD",
        "type": "power_in",
        "description": "1.8V analog supply, bypassed to ground with a 0.1µF ceramic capacitor (pins 1 and 2 may share one capacitor)."
      },
      {
        "number": "3",
        "name": "GND",
        "type": "power_in",
        "description": "Power ground; the exposed pad on the back must be soldered to PCB ground."
      },
      {
        "number": "4",
        "name": "Vin+",
        "type": "power_in",
        "description": "Differential analog input, positive terminal."
      },
      {
        "number": "5",
        "name": "Vin-",
        "type": "power_in",
        "description": "Differential analog input, negative terminal."
      },
      {
        "number": "6",
        "name": "GND",
        "type": "power_in",
        "description": "Power ground; the exposed pad on the back must be soldered to PCB ground."
      },
      {
        "number": "7",
        "name": "SENSE",
        "type": "input",
        "description": "Reference select input: tie to VDD for the internal reference (±0.75V input range), or apply an external 1.2V to 1.3V reference for a ±0.6*VSENSE input range."
      },
      {
        "number": "8",
        "name": "VREF",
        "type": "power_in",
        "description": "Reference voltage output, nominally 1.25V, bypassed to ground with a 2.2µF ceramic capacitor."
      },
      {
        "number": "9",
        "name": "VCM",
        "type": "output",
        "description": "Common-mode bias output, nominally 0.435*VDD, used to set the analog input common mode and bypassed to ground with a 0.1µF ceramic capacitor."
      },
      {
        "number": "10",
        "name": "GND",
        "type": "power_in",
        "description": "Power ground; the exposed pad on the back must be soldered to PCB ground."
      },
      {
        "number": "11",
        "name": "CLK+",
        "type": "input",
        "description": "Clock input; conversion starts on the rising edge."
      },
      {
        "number": "12",
        "name": "CLK-",
        "type": "input",
        "description": "Clock input; conversion starts on the falling edge."
      },
      {
        "number": "13",
        "name": "GND",
        "type": "power_in",
        "description": "Power ground; the exposed pad on the back must be soldered to PCB ground."
      },
      {
        "number": "14",
        "name": "OF-",
        "type": "output",
        "description": "Negative LVDS overflow/underflow output; OF+ is high when overflow or underflow occurs."
      },
      {
        "number": "15",
        "name": "OF+",
        "type": "output",
        "description": "Positive LVDS overflow/underflow output; high when overflow or underflow occurs."
      },
      {
        "number": "16",
        "name": "NC",
        "type": "unconnected",
        "description": "No connect."
      },
      {
        "number": "17",
        "name": "NC",
        "type": "unconnected",
        "description": "No connect."
      },
      {
        "number": "18",
        "name": "D0_1-",
        "type": "output",
        "description": "DDR LVDS output negative, carrying bit D0 when CLKOUT+ is low and D1 when CLKOUT+ is high."
      },
      {
        "number": "19",
        "name": "D0_1+",
        "type": "output",
        "description": "DDR LVDS output positive, carrying bit D0 when CLKOUT+ is low and D1 when CLKOUT+ is high."
      },
      {
        "number": "20",
        "name": "DVDD",
        "type": "power_in",
        "description": "1.8V supply for the digital output drivers, bypassed to ground with its own 0.1µF ceramic capacitor."
      },
      {
        "number": "21",
        "name": "DGND",
        "type": "power_in",
        "description": "Ground for the digital output drivers."
      },
      {
        "number": "22",
        "name": "D2_3-",
        "type": "output",
        "description": "DDR LVDS output negative, carrying bit D2 when CLKOUT+ is low and D3 when CLKOUT+ is high."
      },
      {
        "number": "23",
        "name": "D2_3+",
        "type": "output",
        "description": "DDR LVDS output positive, carrying bit D2 when CLKOUT+ is low and D3 when CLKOUT+ is high."
      },
      {
        "number": "24",
        "name": "D4_5-",
        "type": "output",
        "description": "DDR LVDS output negative, carrying bit D4 when CLKOUT+ is low and D5 when CLKOUT+ is high."
      },
      {
        "number": "25",
        "name": "D4_5+",
        "type": "output",
        "description": "DDR LVDS output positive, carrying bit D4 when CLKOUT+ is low and D5 when CLKOUT+ is high."
      },
      {
        "number": "26",
        "name": "CLKOUT-",
        "type": "output",
        "description": "Negative LVDS data output clock; its phase can be delayed relative to the data via the register settings."
      },
      {
        "number": "27",
        "name": "CLKOUT+",
        "type": "output",
        "description": "Positive LVDS data output clock; LVDS outputs normally transition with its edges, and its phase can be delayed relative to the data via the register settings."
      },
      {
        "number": "28",
        "name": "D6_7-",
        "type": "output",
        "description": "DDR LVDS output negative, carrying bit D6 when CLKOUT+ is low and D7 when CLKOUT+ is high."
      },
      {
        "number": "29",
        "name": "D6_7+",
        "type": "output",
        "description": "DDR LVDS output positive, carrying bit D6 when CLKOUT+ is low and D7 when CLKOUT+ is high."
      },
      {
        "number": "30",
        "name": "DVDD",
        "type": "power_in",
        "description": "1.8V supply for the digital output drivers, bypassed to ground with its own 0.1µF ceramic capacitor."
      },
      {
        "number": "31",
        "name": "D8_9-",
        "type": "output",
        "description": "DDR LVDS output negative, carrying bit D8 when CLKOUT+ is low and D9 when CLKOUT+ is high."
      },
      {
        "number": "32",
        "name": "D8_9+",
        "type": "output",
        "description": "DDR LVDS output positive, carrying bit D8 when CLKOUT+ is low and D9 when CLKOUT+ is high."
      },
      {
        "number": "33",
        "name": "D10_11-",
        "type": "output",
        "description": "DDR LVDS output negative, carrying bit D10 when CLKOUT+ is low and D11 when CLKOUT+ is high."
      },
      {
        "number": "34",
        "name": "D10_11+",
        "type": "output",
        "description": "DDR LVDS output positive, carrying bit D10 when CLKOUT+ is low and D11 when CLKOUT+ is high."
      },
      {
        "number": "35",
        "name": "GND",
        "type": "power_in",
        "description": "Power ground; the exposed pad on the back must be soldered to PCB ground."
      },
      {
        "number": "36",
        "name": "SPI_MISO",
        "type": "output",
        "description": "SPI MISO in serial mode (MODE=0), open-drain and needing a 2k pull-up to the 1.8V to 3.3V SPI supply for readback; no function in parallel mode."
      },
      {
        "number": "37",
        "name": "SPI_MOSI",
        "type": "input",
        "description": "SPI MOSI in serial mode (MODE=0); in parallel mode (MODE=VDD) selects LVDS drive current: 0 = 3.5mA, 1 (1.8V to 3.3V) = 1.75mA."
      },
      {
        "number": "38",
        "name": "SPI_SCLK",
        "type": "input",
        "description": "SPI SCLK in serial mode (MODE=0); in parallel mode selects sleep: 0 = normal operation, 1 (1.8V to 3.3V) = sleep (AC power down)."
      },
      {
        "number": "39",
        "name": "SPI_CS",
        "type": "input",
        "description": "SPI chip select in serial mode (MODE=0); in parallel mode controls the clock duty cycle stabilizer: 0 = off, 1 (1.8V to 3.3V) = on."
      },
      {
        "number": "40",
        "name": "MODE",
        "type": "input",
        "description": "Serial/parallel mode select: tie to GND for SPI mode or to VDD for parallel GPIO mode, connected directly and not driven by a logic signal."
      },
      {
        "number": "41",
        "name": "EP",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-sonnet-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The exposed pad has no pin number in the datasheet. 'EP' is used as the identifier. The text says it; Pins 16 and 17 are labelled NC only in the package figure, not in the pin table. The datasheet gives; The pin table prints the clock output name as 'CKLOUT-'. It is read here as CLKOUT-, matching the fi"
        ],
        "pages_sent": 19,
        "cost_usd": 0.2313,
        "at": "2026-10-30T16:44:33"
      },
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/fa73fdff2dfb7a384e2b258cf574a00c.pdf",
        "pages": 19,
        "sha256": "926694c566e99cdc",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 41,
        "described": 41,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "zgad250s12.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          6.0,
          1.0
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "e5b4286c2329085d9ef7f90d5eb5bf41a435241ecc1baaf1383823b6d6a946ae",
        "checked": "2026-10-30",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "zgad250s12-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          6.0,
          1.0
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "e98dea79f3d82e0f3c05700e5a737fcc193557f9fd61ffbf815a2c6e26c319a1",
        "checked": "2026-10-30",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ],
    "package_dims": {
      "package_code": "QFN40",
      "source_page": 18,
      "e": {
        "nom_mm": 0.5,
        "range_mm": [
          null,
          null
        ]
      },
      "source": "datasheet package drawing, every number found on its page (extract_pins --task dims)",
      "model_check": {
        "file": "zgad250s12.step",
        "verdict": "SKIP",
        "reasons": [
          "the datasheet dimensions give no height or body size to compare"
        ],
        "by": "factory/package_fit.py"
      }
    }
  }
}