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ZGAD250S12

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Zynalog Analog To Digital Converters (ADCs), QFN-40(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionzgad250s12factory-2.0.0extractor-text

Verified ZGAD250S12

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier lcsc, 41 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ZGAD250S12 · QFN-40(6x6) · 41 pins
  • ✓copper: 41 copper pads, none touching another net
  • ✓datasheet: all 41 pin names found in the 19-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-mrc15v6w/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): the datasheet dimensions give no height or body size to compare (datasheet p.18)
  • ✓pads: 41 pins = 41 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 41 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ zgad250s12.kicad_sym✓ zgad250s12.kicad_mod✓ zgad250s12.step
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ZGAD250S12

Zynalog · Analog To Digital Converters (ADCs) · QFN-40(6x6)

ZGAD250S12 from Zynalog, in a QFN-40(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in 1.8V analog supply, bypassed to ground with a 0.1µF ceramic capacitor (pins 1 and 2 may share one capacitor).
2 VDD power_in 1.8V analog supply, bypassed to ground with a 0.1µF ceramic capacitor (pins 1 and 2 may share one capacitor).
3 GND power_in Power ground; the exposed pad on the back must be soldered to PCB ground.
4 Vin+ power_in Differential analog input, positive terminal.
5 Vin- power_in Differential analog input, negative terminal.
6 GND power_in Power ground; the exposed pad on the back must be soldered to PCB ground.
7 SENSE input Reference select input: tie to VDD for the internal reference (±0.75V input range), or apply an external 1.2V to 1.3V reference for a ±0.6*VSENSE input range.
8 VREF power_in Reference voltage output, nominally 1.25V, bypassed to ground with a 2.2µF ceramic capacitor.
9 VCM output Common-mode bias output, nominally 0.435*VDD, used to set the analog input common mode and bypassed to ground with a 0.1µF ceramic capacitor.
10 GND power_in Power ground; the exposed pad on the back must be soldered to PCB ground.
11 CLK+ input Clock input; conversion starts on the rising edge.
12 CLK- input Clock input; conversion starts on the falling edge.
13 GND power_in Power ground; the exposed pad on the back must be soldered to PCB ground.
14 OF- output Negative LVDS overflow/underflow output; OF+ is high when overflow or underflow occurs.
15 OF+ output Positive LVDS overflow/underflow output; high when overflow or underflow occurs.
16 NC unconnected No connect.
17 NC unconnected No connect.
18 D0_1- output DDR LVDS output negative, carrying bit D0 when CLKOUT+ is low and D1 when CLKOUT+ is high.
19 D0_1+ output DDR LVDS output positive, carrying bit D0 when CLKOUT+ is low and D1 when CLKOUT+ is high.
20 DVDD power_in 1.8V supply for the digital output drivers, bypassed to ground with its own 0.1µF ceramic capacitor.
21 DGND power_in Ground for the digital output drivers.
22 D2_3- output DDR LVDS output negative, carrying bit D2 when CLKOUT+ is low and D3 when CLKOUT+ is high.
23 D2_3+ output DDR LVDS output positive, carrying bit D2 when CLKOUT+ is low and D3 when CLKOUT+ is high.
24 D4_5- output DDR LVDS output negative, carrying bit D4 when CLKOUT+ is low and D5 when CLKOUT+ is high.
25 D4_5+ output DDR LVDS output positive, carrying bit D4 when CLKOUT+ is low and D5 when CLKOUT+ is high.
26 CLKOUT- output Negative LVDS data output clock; its phase can be delayed relative to the data via the register settings.
27 CLKOUT+ output Positive LVDS data output clock; LVDS outputs normally transition with its edges, and its phase can be delayed relative to the data via the register settings.
28 D6_7- output DDR LVDS output negative, carrying bit D6 when CLKOUT+ is low and D7 when CLKOUT+ is high.
29 D6_7+ output DDR LVDS output positive, carrying bit D6 when CLKOUT+ is low and D7 when CLKOUT+ is high.
30 DVDD power_in 1.8V supply for the digital output drivers, bypassed to ground with its own 0.1µF ceramic capacitor.
31 D8_9- output DDR LVDS output negative, carrying bit D8 when CLKOUT+ is low and D9 when CLKOUT+ is high.
32 D8_9+ output DDR LVDS output positive, carrying bit D8 when CLKOUT+ is low and D9 when CLKOUT+ is high.
33 D10_11- output DDR LVDS output negative, carrying bit D10 when CLKOUT+ is low and D11 when CLKOUT+ is high.
34 D10_11+ output DDR LVDS output positive, carrying bit D10 when CLKOUT+ is low and D11 when CLKOUT+ is high.
35 GND power_in Power ground; the exposed pad on the back must be soldered to PCB ground.
36 SPI_MISO output SPI MISO in serial mode (MODE=0), open-drain and needing a 2k pull-up to the 1.8V to 3.3V SPI supply for readback; no function in parallel mode.
37 SPI_MOSI input SPI MOSI in serial mode (MODE=0); in parallel mode (MODE=VDD) selects LVDS drive current: 0 = 3.5mA, 1 (1.8V to 3.3V) = 1.75mA.
38 SPI_SCLK input SPI SCLK in serial mode (MODE=0); in parallel mode selects sleep: 0 = normal operation, 1 (1.8V to 3.3V) = sleep (AC power down).
39 SPI_CS input SPI chip select in serial mode (MODE=0); in parallel mode controls the clock duty cycle stabilizer: 0 = off, 1 (1.8V to 3.3V) = on.
40 MODE input Serial/parallel mode select: tie to GND for SPI mode or to VDD for parallel GPIO mode, connected directly and not driven by a logic signal.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Zynalog
Package QFN-40(6x6)
Category ADC/DAC/Data Conversion
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Analog supply voltage VDD 1.7 1.8 1.9 V 4
Digital supply voltage DVDD 1.7 1.8 1.9 V 4
Analog supply current I_VDD 165 168 mA 4
Integral nonlinearity INL -2 0.6 2 LSB 4
Differential nonlinearity DNL -0.6 0.25 0.6 LSB 4
Offset error Offset Error -13 5 13 mV 4
Gain error Gain Error -4 1 2.2 %FS 4
Digital output differential voltage (3.5mA mode) V_OD 247 350 454 mV 3.5mA mode 4
Digital output differential voltage (1.75mA mode) V_OD 125 175 250 mV 1.75mA mode 4
Digital output common-mode voltage V_OS 1.125 1.25 1.375 V 4
Supply voltage range VDD,DVDD -0.3 2 V 6
Analog input voltage range Analog Vin -0.3 V -0.3 to VDD+0.2 6
CLK,SENSE input voltage range CLK,SENSE -0.3 V -0.3 to VDD+0.2 6
SPI/GPIO digital voltage range SPI 3.9 V VDD to 3.9 6
LVDS output digital voltage range Data Output -0.3 V -0.3 to DVDD+0.2 6
Operating temperature WORKING TEMP -40 85 °C 6
Storage temperature STORAGE TEMP -65 150 °C 6
Clock input high hold time tH 1.9 2 ns VDD=1.8V, DVDD=1.8V, fS=250MHz 10
Clock input low hold time tL 1.9 2 ns VDD=1.8V, DVDD=1.8V, fS=250MHz 10
Clock input to clock output delay tC 1.3 1.6 2 ns VDD=1.8V, DVDD=1.8V, fS=250MHz 10
Clock input to data output delay tD 1.7 2 2.3 ns VDD=1.8V, DVDD=1.8V, fS=250MHz 10
Clock output to data output skew (tC-tD) tSKEW 0.3 0.4 0.55 ns VDD=1.8V, DVDD=1.8V, fS=250MHz 10
CS low to clock setup time tS 5 ns SPI_MISO pull-up 2KΩ 15
Data setup time tDS 5 ns SPI_MISO pull-up 2KΩ 15
Data hold time tDH 5 ns SPI_MISO pull-up 2KΩ 15
Clock to data output delay tDO 125 ns SPI_MISO pull-up 2KΩ 15
Clock period (write) tSCK 40 ns SPI_MISO pull-up 2KΩ 15
Clock period (readback) tSCK 250 ns SPI_MISO pull-up 2KΩ 15
Clock to CS high hold time tH 5 ns SPI_MISO pull-up 2KΩ 15
Digital supply current I_DVDD 37 mA 4
Power with 1.75mA LVDS output P_1.75 328 mW 1.75mA LVDS output 4
Power with 3.5mA LVDS output P_3.5 362 mW 3.5mA LVDS output 4
Low power mode power P_lowpower 102.5 mW 4
Sleep mode power P_sleep 0.65 mW 4
Clock input to data acquisition delay tAP 1 ns VDD=1.8V, DVDD=1.8V, fS=250MHz 10

CAD (KiCad official)

  • Symbol: ZGAD250S12
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: QFN-40(6x6) (KiCad packages3D, STEP)
  • 3D model files: zgad250s12-etched.step / zgad250s12-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); zgad250s12.step / zgad250s12.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Zynalog datasheet (19 pp, sha256 926694c566e99cdc, retrieved 2026-10-30, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF