component
ZGAD250D14
Public Made by Adomby adom
Zynalog Analog To Digital Converters (ADCs), QFN-64(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895
{
"schema_version": 1,
"type": "component",
"slug": "zgad250d14",
"title": "ZGAD250D14",
"brief": "Zynalog Analog To Digital Converters (ADCs), QFN-64(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"version": "0.1.0",
"license": "CC-BY-SA-4.0",
"tags": [
"component",
"adc-dac-data conversion",
"zgad250d14",
"factory-2.0.0",
"extractor-text"
],
"component": {
"mpn": "ZGAD250D14",
"manufacturer": "Zynalog",
"package": "QFN-64(9x9)",
"pin_count": 65,
"category": "ADC/DAC/Data Conversion",
"subcategory": "Analog To Digital Converters (ADCs)",
"datasheet": "https://datasheet.lcsc.com/datasheet/pdf/fe7f64d7964415288aacae79074c1bdf.pdf",
"parts": {
"symbol": "zgad250d14.kicad_sym",
"footprint": "zgad250d14.kicad_mod",
"model_3d": "zgad250d14-hero.glb",
"model_3d_plain": "zgad250d14-etched.glb",
"model_3d_step": "zgad250d14-etched.step",
"model_3d_step_plain": "zgad250d14.step",
"lbr": "zgad250d14.lbr"
},
"distributor_links": {
"lcsc": "C7527744"
},
"distributor_check": {
"checked_at": "2026-11-02T17:04:33Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": null,
"status": "no match"
},
"mouser": {
"pn": null,
"status": "no match"
}
},
"pins": [
{
"number": "1",
"name": "VDD",
"type": "power_in",
"description": "1.8V analog supply, bypassed to ground with 0.1uF ceramic capacitor; pins 1, 2 and 64 may share one bypass capacitor."
},
{
"number": "2",
"name": "VDD",
"type": "power_in",
"description": "1.8V analog supply, bypassed to ground with 0.1uF ceramic capacitor; may share the bypass capacitor with pins 1 and 64."
},
{
"number": "3",
"name": "GND",
"type": "power_in",
"description": "Power ground; the exposed pad on the package underside must be soldered to the PCB ground."
},
{
"number": "4",
"name": "VinA+",
"type": "input",
"description": "Channel A differential analog input positive; the differential input voltage should be kept within 1.5V and the two inputs should be 180 degrees out of phase."
},
{
"number": "5",
"name": "VinA-",
"type": "input",
"description": "Channel A differential analog input negative; the differential input voltage should be kept within 1.5V and the two inputs should be 180 degrees out of phase."
},
{
"number": "6",
"name": "GND",
"type": "power_in",
"description": "Power ground; the exposed pad on the package underside must be soldered to the PCB ground."
},
{
"number": "7",
"name": "SENSE",
"type": "input",
"description": "External reference input; connecting it to VDD selects the internal reference with a +/-0.75V input range, while an external reference of 1.2V to 1.3V gives a +/-0.6*VSENSE input range."
},
{
"number": "8",
"name": "VREF",
"type": "power_in",
"description": "Reference voltage output, nominally 1.25V, bypassed to ground with a 2.2uF ceramic capacitor."
},
{
"number": "9",
"name": "GND",
"type": "power_in",
"description": "Power ground; the exposed pad on the package underside must be soldered to the PCB ground."
},
{
"number": "10",
"name": "VCM",
"type": "output",
"description": "Common-mode bias output, nominally 0.435*VDD, used to set the common-mode bias of the analog inputs and bypassed to ground with a 0.1uF ceramic capacitor."
},
{
"number": "11",
"name": "GND",
"type": "power_in",
"description": "Power ground; the exposed pad on the package underside must be soldered to the PCB ground."
},
{
"number": "12",
"name": "VinB-",
"type": "input",
"description": "Channel B differential analog input negative; the differential input voltage should be kept within 1.5V and the two inputs should be 180 degrees out of phase."
},
{
"number": "13",
"name": "VinB+",
"type": "input",
"description": "Channel B differential analog input positive; the differential input voltage should be kept within 1.5V and the two inputs should be 180 degrees out of phase."
},
{
"number": "14",
"name": "GND",
"type": "power_in",
"description": "Power ground; the exposed pad on the package underside must be soldered to the PCB ground."
},
{
"number": "15",
"name": "VDD",
"type": "power_in",
"description": "1.8V analog supply, bypassed to ground with 0.1uF ceramic capacitor; pins 15, 16 and 17 may share one bypass capacitor."
},
{
"number": "16",
"name": "VDD",
"type": "power_in",
"description": "1.8V analog supply, bypassed to ground with 0.1uF ceramic capacitor; may share the bypass capacitor with pins 15 and 17."
},
{
"number": "17",
"name": "VDD",
"type": "power_in",
"description": "1.8V analog supply, bypassed to ground with 0.1uF ceramic capacitor; may share the bypass capacitor with pins 15 and 16."
},
{
"number": "18",
"name": "GND",
"type": "power_in",
"description": "Power ground; the exposed pad on the package underside must be soldered to the PCB ground."
},
{
"number": "19",
"name": "CLK+",
"type": "input",
"description": "Differential clock input positive; conversion starts on the rising edge of the clock."
},
{
"number": "20",
"name": "CLK-",
"type": "input",
"description": "Differential clock input negative; conversion starts on the falling edge of the clock."
},
{
"number": "21",
"name": "GND",
"type": "power_in",
"description": "Power ground; the exposed pad on the package underside must be soldered to the PCB ground."
},
{
"number": "22",
"name": "OF-",
"type": "output",
"description": "Overflow/underflow LVDS output, negative leg; OF+ is high when an overflow or underflow occurs, and channel A and B overflow flags are multiplexed onto this pair."
},
{
"number": "23",
"name": "OF+",
"type": "output",
"description": "Overflow/underflow LVDS output, positive leg; high when an overflow or underflow occurs, and channel A and B overflow flags are multiplexed onto this pair."
},
{
"number": "24",
"name": "DB0_1-",
"type": "output",
"description": "Channel B DDR LVDS output negative leg carrying bit D0 while CLKOUT+ is low and bit D1 while CLKOUT+ is high."
},
{
"number": "25",
"name": "DB0_1+",
"type": "output",
"description": "Channel B DDR LVDS output positive leg carrying bit D0 while CLKOUT+ is low and bit D1 while CLKOUT+ is high."
},
{
"number": "26",
"name": "DB2_3-",
"type": "output",
"description": "Channel B DDR LVDS output negative leg carrying bit D2 while CLKOUT+ is low and bit D3 while CLKOUT+ is high."
},
{
"number": "27",
"name": "DB2_3+",
"type": "output",
"description": "Channel B DDR LVDS output positive leg carrying bit D2 while CLKOUT+ is low and bit D3 while CLKOUT+ is high."
},
{
"number": "28",
"name": "DB4_5-",
"type": "output",
"description": "Channel B DDR LVDS output negative leg carrying bit D4 while CLKOUT+ is low and bit D5 while CLKOUT+ is high."
},
{
"number": "29",
"name": "DB4_5+",
"type": "output",
"description": "Channel B DDR LVDS output positive leg carrying bit D4 while CLKOUT+ is low and bit D5 while CLKOUT+ is high."
},
{
"number": "30",
"name": "DB6_7-",
"type": "output",
"description": "Channel B DDR LVDS output negative leg carrying bit D6 while CLKOUT+ is low and bit D7 while CLKOUT+ is high."
},
{
"number": "31",
"name": "DB6_7+",
"type": "output",
"description": "Channel B DDR LVDS output positive leg carrying bit D6 while CLKOUT+ is low and bit D7 while CLKOUT+ is high."
},
{
"number": "32",
"name": "DVDD",
"type": "power_in",
"description": "1.8V supply for the digital output drivers, bypassed to ground with a separate 0.1uF ceramic capacitor per pin."
},
{
"number": "33",
"name": "DGND",
"type": "power_in",
"description": "Ground for the digital output drivers."
},
{
"number": "34",
"name": "DB8_9-",
"type": "output",
"description": "Channel B DDR LVDS output negative leg carrying bit D8 while CLKOUT+ is low and bit D9 while CLKOUT+ is high."
},
{
"number": "35",
"name": "DB8_9+",
"type": "output",
"description": "Channel B DDR LVDS output positive leg carrying bit D8 while CLKOUT+ is low and bit D9 while CLKOUT+ is high."
},
{
"number": "36",
"name": "DB10_11-",
"type": "output",
"description": "Channel B DDR LVDS output negative leg carrying bit D10 while CLKOUT+ is low and bit D11 while CLKOUT+ is high."
},
{
"number": "37",
"name": "DB10_11+",
"type": "output",
"description": "Channel B DDR LVDS output positive leg carrying bit D10 while CLKOUT+ is low and bit D11 while CLKOUT+ is high."
},
{
"number": "38",
"name": "DB12_13-",
"type": "output",
"description": "Channel B DDR LVDS output negative leg carrying bit D12 while CLKOUT+ is low and bit D13 while CLKOUT+ is high."
},
{
"number": "39",
"name": "DB12_13+",
"type": "output",
"description": "Channel B DDR LVDS output positive leg carrying bit D12 while CLKOUT+ is low and bit D13 while CLKOUT+ is high."
},
{
"number": "40",
"name": "CLKOUT-",
"type": "output",
"description": "Data output clock LVDS negative leg, which normally transitions together with the data outputs; its phase can be delayed relative to the data through the timing register."
},
{
"number": "41",
"name": "CLKOUT+",
"type": "output",
"description": "Data output clock LVDS positive leg, which normally transitions together with the data outputs; its phase can be delayed relative to the data through the timing register."
},
{
"number": "42",
"name": "DA0_1-",
"type": "output",
"description": "Channel A DDR LVDS output negative leg carrying bit D0 while CLKOUT+ is low and bit D1 while CLKOUT+ is high."
},
{
"number": "43",
"name": "DA0_1+",
"type": "output",
"description": "Channel A DDR LVDS output positive leg carrying bit D0 while CLKOUT+ is low and bit D1 while CLKOUT+ is high."
},
{
"number": "44",
"name": "DA2_3-",
"type": "output",
"description": "Channel A DDR LVDS output negative leg carrying bit D2 while CLKOUT+ is low and bit D3 while CLKOUT+ is high."
},
{
"number": "45",
"name": "DA2_3+",
"type": "output",
"description": "Channel A DDR LVDS output positive leg carrying bit D2 while CLKOUT+ is low and bit D3 while CLKOUT+ is high."
},
{
"number": "46",
"name": "DA4_5-",
"type": "output",
"description": "Channel A DDR LVDS output negative leg carrying bit D4 while CLKOUT+ is low and bit D5 while CLKOUT+ is high."
},
{
"number": "47",
"name": "DA4_5+",
"type": "output",
"description": "Channel A DDR LVDS output positive leg carrying bit D4 while CLKOUT+ is low and bit D5 while CLKOUT+ is high."
},
{
"number": "48",
"name": "DGND",
"type": "power_in",
"description": "Ground for the digital output drivers."
},
{
"number": "49",
"name": "DVDD",
"type": "power_in",
"description": "1.8V supply for the digital output drivers, bypassed to ground with a separate 0.1uF ceramic capacitor per pin."
},
{
"number": "50",
"name": "DA6_7-",
"type": "output",
"description": "Channel A DDR LVDS output negative leg carrying bit D6 while CLKOUT+ is low and bit D7 while CLKOUT+ is high."
},
{
"number": "51",
"name": "DA6_7+",
"type": "output",
"description": "Channel A DDR LVDS output positive leg carrying bit D6 while CLKOUT+ is low and bit D7 while CLKOUT+ is high."
},
{
"number": "52",
"name": "DA8_9-",
"type": "output",
"description": "Channel A DDR LVDS output negative leg carrying bit D8 while CLKOUT+ is low and bit D9 while CLKOUT+ is high."
},
{
"number": "53",
"name": "DA8_9+",
"type": "output",
"description": "Channel A DDR LVDS output positive leg carrying bit D8 while CLKOUT+ is low and bit D9 while CLKOUT+ is high."
},
{
"number": "54",
"name": "DA10_11-",
"type": "output",
"description": "Channel A DDR LVDS output negative leg carrying bit D10 while CLKOUT+ is low and bit D11 while CLKOUT+ is high."
},
{
"number": "55",
"name": "DA10_11+",
"type": "output",
"description": "Channel A DDR LVDS output positive leg carrying bit D10 while CLKOUT+ is low and bit D11 while CLKOUT+ is high."
},
{
"number": "56",
"name": "DA12_13-",
"type": "output",
"description": "Channel A DDR LVDS output negative leg carrying bit D12 while CLKOUT+ is low and bit D13 while CLKOUT+ is high."
},
{
"number": "57",
"name": "DA12_13+",
"type": "output",
"description": "Channel A DDR LVDS output positive leg carrying bit D12 while CLKOUT+ is low and bit D13 while CLKOUT+ is high."
},
{
"number": "58",
"name": "GND",
"type": "power_in",
"description": "Power ground; the exposed pad on the package underside must be soldered to the PCB ground."
},
{
"number": "59",
"name": "SPI_MISO",
"type": "output",
"description": "SPI data readback output in serial mode (MODE=0), open-drain and requiring a 2K pull-up to the 1.8V to 3.3V SPI supply when registers are read back; no function in parallel mode."
},
{
"number": "60",
"name": "SPI_MOSI",
"type": "input",
"description": "SPI data input in serial mode (MODE=0); in parallel mode (MODE=VDD) it selects LVDS output current, 3.5mA when low and 1.75mA when high at 1.8V to 3.3V logic levels."
},
{
"number": "61",
"name": "SPI_SCLK",
"type": "input",
"description": "SPI clock input in serial mode (MODE=0); in parallel mode (MODE=VDD) it enables sleep mode when high at 1.8V to 3.3V logic levels."
},
{
"number": "62",
"name": "SPI_CS",
"type": "input",
"description": "SPI chip select in serial mode (MODE=0); in parallel mode (MODE=VDD) it enables the clock duty cycle stabilizer when high at 1.8V to 3.3V logic levels."
},
{
"number": "63",
"name": "MODE",
"type": "input",
"description": "Serial/parallel interface mode select; connect directly to GND for SPI mode or to VDD for parallel GPIO mode and do not drive it with a logic signal."
},
{
"number": "64",
"name": "VDD",
"type": "power_in",
"description": "1.8V analog supply, bypassed to ground with 0.1uF ceramic capacitor; may share the bypass capacitor with pins 1 and 2."
},
{
"number": "65",
"name": "EP",
"type": "passive",
"description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The ordering table (page 13) lists ZGAD250D14 as QFN64 DDR LVDS, matching the QFN-64 (9x9) hint. Pin"
],
"pages_sent": 19,
"cost_usd": 0.0598,
"at": "2026-11-02T17:04:08"
},
"datasheet": {
"url": "https://datasheet.lcsc.com/datasheet/pdf/fe7f64d7964415288aacae79074c1bdf.pdf",
"pages": 19,
"sha256": "60a81de455573fc7",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 65,
"described": 65,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "zgad250d14.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
9,
9,
0.75
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "dce07a86ec3fe3ca87eebdff13827f55e036ced5518fee01f85cec4a3f56366d",
"checked": "2026-11-02",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "zgad250d14-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
9,
9,
0.75
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "c8e6ed4e7910f33de920bead38f2c83b6a43db0fa97885b37b3aed85dfbe9903",
"checked": "2026-11-02",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
},
"metadata": {
"specs": {
"Manufacturer": "Zynalog",
"Package": "QFN-64(9x9)",
"Category": "ADC/DAC/Data Conversion",
"Pins": "65"
},
"characteristics": {
"version": 1,
"source": "datasheet",
"datasheet_sha256": "60a81de455573fc7791a939f3a6d4098307ac75eaf01bd16ea3f260779af95a5",
"rows": [
{
"name": "Analog supply voltage",
"symbol": "VDD",
"kind": "electrical",
"unit": "V",
"min": 1.7,
"typ": 1.8,
"max": 1.9,
"conditions": "",
"source_page": 4,
"source": "datasheet"
},
{
"name": "Digital supply voltage",
"symbol": "DVDD",
"kind": "electrical",
"unit": "V",
"min": 1.7,
"typ": 1.8,
"max": 1.9,
"conditions": "",
"source_page": 4,
"source": "datasheet"
},
{
"name": "Analog supply input current",
"symbol": "I_VDD",
"kind": "electrical",
"unit": "mA",
"min": null,
"typ": 280,
"max": 290,
"conditions": "",
"source_page": 4,
"source": "datasheet"
},
{
"name": "Digital supply input current",
"symbol": "I_DVDD",
"kind": "electrical",
"unit": "mA",
"min": null,
"typ": null,
"max": 64,
"conditions": "",
"source_page": 4,
"source": "datasheet"
},
{
"name": "Power dissipation, LVDS output 1.75mA, both channels on",
"symbol": "P_1.75",
"kind": "electrical",
"unit": "mW",
"min": null,
"typ": null,
"max": 580,
"conditions": "1.75mA LVDS output, both channels on",
"source_page": 4,
"source": "datasheet"
},
{
"name": "Power dissipation, LVDS output 3.5mA, both channels on",
"symbol": "P_3.5",
"kind": "electrical",
"unit": "mW",
"min": null,
"typ": null,
"max": 620,
"conditions": "3.5mA LVDS output, both channels on",
"source_page": 4,
"source": "datasheet"
},
{
"name": "Power dissipation, sleep mode",
"symbol": "P_sleep",
"kind": "electrical",
"unit": "mW",
"min": null,
"typ": null,
"max": 0.65,
"conditions": "睡眠模式",
"source_page": 4,
"source": "datasheet"
},
{
"name": "Integral nonlinearity",
"symbol": "INL",
"kind": "electrical",
"unit": "LSB",
"min": -2,
"typ": 1,
"max": 2,
"conditions": "",
"source_page": 4,
"source": "datasheet"
},
{
"name": "Differential nonlinearity",
"symbol": "DNL",
"kind": "electrical",
"unit": "LSB",
"min": -0.6,
"typ": 0.35,
"max": 0.6,
"conditions": "",
"source_page": 4,
"source": "datasheet"
},
{
"name": "Offset error",
"symbol": "",
"kind": "electrical",
"unit": "mV",
"min": -13,
"typ": 5,
"max": 13,
"conditions": "",
"source_page": 4,
"source": "datasheet"
},
{
"name": "Gain error",
"symbol": "",
"kind": "electrical",
"unit": "%FS",
"min": -4,
"typ": 1,
"max": 2.2,
"conditions": "",
"source_page": 4,
"source": "datasheet"
},
{
"name": "LVDS differential output voltage, 3.5mA mode",
"symbol": "V_OD",
"kind": "electrical",
"unit": "mV",
"min": 247,
"typ": 350,
"max": 454,
"conditions": "3.5mA模式下",
"source_page": 4,
"source": "datasheet"
},
{
"name": "LVDS differential output voltage, 1.75mA mode",
"symbol": "V_OD",
"kind": "electrical",
"unit": "mV",
"min": 125,
"typ": 175,
"max": 250,
"conditions": "1.75mA模式下",
"source_page": 4,
"source": "datasheet"
},
{
"name": "LVDS output common-mode voltage",
"symbol": "V_OS",
"kind": "electrical",
"unit": "V",
"min": 1.125,
"typ": 1.25,
"max": 1.375,
"conditions": "",
"source_page": 4,
"source": "datasheet"
},
{
"name": "Clock input to clock output delay",
"symbol": "tC",
"kind": "timing",
"unit": "ns",
"min": 1.3,
"typ": 1.6,
"max": 2,
"conditions": "VDD=1.8V, DVDD=1.8V, fS=250MHz",
"source_page": 10,
"source": "datasheet"
},
{
"name": "Clock input to data output delay",
"symbol": "tD",
"kind": "timing",
"unit": "ns",
"min": 1.7,
"typ": 2,
"max": 2.3,
"conditions": "VDD=1.8V, DVDD=1.8V, fS=250MHz",
"source_page": 10,
"source": "datasheet"
},
{
"name": "Clock output to data output skew (tC - tD)",
"symbol": "tSKEW",
"kind": "timing",
"unit": "ns",
"min": 0.3,
"typ": 0.4,
"max": 0.55,
"conditions": "VDD=1.8V, DVDD=1.8V, fS=250MHz",
"source_page": 10,
"source": "datasheet"
},
{
"name": "Maximum input voltage range, VDD and DVDD",
"symbol": "VDD,DVDD",
"kind": "absolute_maximum",
"unit": "V",
"min": -0.3,
"typ": null,
"max": 2,
"conditions": "",
"source_page": 6,
"source": "datasheet"
},
{
"name": "Maximum analog input voltage range",
"symbol": "Analog Vin",
"kind": "absolute_maximum",
"unit": "V",
"min": -0.3,
"typ": null,
"max": null,
"conditions": "max printed as VDD+0.2",
"source_page": 6,
"source": "datasheet"
},
{
"name": "Maximum input voltage range, CLK and SENSE",
"symbol": "CLK,SENSE",
"kind": "absolute_maximum",
"unit": "V",
"min": -0.3,
"typ": null,
"max": null,
"conditions": "max printed as VDD+0.2",
"source_page": 6,
"source": "datasheet"
},
{
"name": "Maximum SPI/GPIO digital voltage range",
"symbol": "SPI",
"kind": "absolute_maximum",
"unit": "V",
"min": null,
"typ": null,
"max": 3.9,
"conditions": "min printed as VDD",
"source_page": 6,
"source": "datasheet"
},
{
"name": "Maximum LVDS output digital voltage range",
"symbol": "Data Output",
"kind": "absolute_maximum",
"unit": "V",
"min": -0.3,
"typ": null,
"max": null,
"conditions": "max printed as DVDD+0.2",
"source_page": 6,
"source": "datasheet"
},
{
"name": "Working temperature",
"symbol": "",
"kind": "recommended_operating",
"unit": "°C",
"min": -40,
"typ": null,
"max": 85,
"conditions": "",
"source_page": 6,
"source": "datasheet"
},
{
"name": "Storage temperature",
"symbol": "",
"kind": "absolute_maximum",
"unit": "°C",
"min": -65,
"typ": null,
"max": 150,
"conditions": "",
"source_page": 6,
"source": "datasheet"
},
{
"name": "Power dissipation, low power mode",
"symbol": "P_lowpower",
"kind": "electrical",
"unit": "mW",
"min": null,
"typ": 180,
"max": null,
"conditions": "低功耗模式",
"source_page": 4,
"source": "datasheet"
},
{
"name": "Signal-to-noise ratio",
"symbol": "SNR",
"kind": "electrical",
"unit": "dB",
"min": null,
"typ": 70,
"max": null,
"conditions": "",
"source_page": 4,
"source": "datasheet"
},
{
"name": "Spurious-free dynamic range",
"symbol": "SFDR",
"kind": "electrical",
"unit": "dB",
"min": null,
"typ": 90,
"max": null,
"conditions": "",
"source_page": 4,
"source": "datasheet"
}
]
}
},
"variants": [],
"sections": [
"hero",
"viewers",
"readme",
"breadcrumbs",
"info"
],
"discovery_triggers": [
"zgad250d14"
],
"discovery_pitch": "ZGAD250D14 (Zynalog) component page: datasheet pinout, KiCad symbol, footprint and 3D.",
"author": {
"name": "Ray",
"email": "[email protected]"
},
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"zgad250d14.kicad_sym",
"zgad250d14.kicad_mod",
"zgad250d14.glb",
"zgad250d14.step",
"zgad250d14.lbr",
"docs/hero.png",
"docs/zgad250d14-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"zgad250d14-hero.glb",
"zgad250d14-hero.overlay.json",
"zgad250d14-etched.glb"
],
"visibility": {
"public": true
}
}