ZGAD250D14

{
  "slug": "zgad250d14",
  "version": "0.1.0",
  "type": "component",
  "description": "Zynalog Analog To Digital Converters (ADCs), QFN-64(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "adc-dac-data conversion",
    "zgad250d14",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
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    "path": "docs/hero.png"
  },
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    "README.md",
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    "zgad250d14.kicad_mod",
    "zgad250d14.glb",
    "zgad250d14.step",
    "zgad250d14.lbr",
    "docs/hero.png",
    "docs/zgad250d14-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "zgad250d14-hero.glb",
    "zgad250d14-hero.overlay.json",
    "zgad250d14-etched.glb"
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  "component": {
    "mpn": "ZGAD250D14",
    "manufacturer": "Zynalog",
    "package": "QFN-64(9x9)",
    "pin_count": 65,
    "category": "ADC/DAC/Data Conversion",
    "subcategory": "Analog To Digital Converters (ADCs)",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/fe7f64d7964415288aacae79074c1bdf.pdf",
    "parts": {
      "symbol": "zgad250d14.kicad_sym",
      "footprint": "zgad250d14.kicad_mod",
      "model_3d": "zgad250d14-hero.glb",
      "model_3d_plain": "zgad250d14-etched.glb",
      "model_3d_step": "zgad250d14-etched.step",
      "model_3d_step_plain": "zgad250d14.step",
      "lbr": "zgad250d14.lbr"
    },
    "distributor_links": {
      "lcsc": "C7527744"
    },
    "distributor_check": {
      "checked_at": "2026-11-02T17:04:33Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "no match"
      },
      "mouser": {
        "pn": null,
        "status": "no match"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VDD",
        "type": "power_in",
        "description": "1.8V analog supply, bypassed to ground with 0.1uF ceramic capacitor; pins 1, 2 and 64 may share one bypass capacitor."
      },
      {
        "number": "2",
        "name": "VDD",
        "type": "power_in",
        "description": "1.8V analog supply, bypassed to ground with 0.1uF ceramic capacitor; may share the bypass capacitor with pins 1 and 64."
      },
      {
        "number": "3",
        "name": "GND",
        "type": "power_in",
        "description": "Power ground; the exposed pad on the package underside must be soldered to the PCB ground."
      },
      {
        "number": "4",
        "name": "VinA+",
        "type": "input",
        "description": "Channel A differential analog input positive; the differential input voltage should be kept within 1.5V and the two inputs should be 180 degrees out of phase."
      },
      {
        "number": "5",
        "name": "VinA-",
        "type": "input",
        "description": "Channel A differential analog input negative; the differential input voltage should be kept within 1.5V and the two inputs should be 180 degrees out of phase."
      },
      {
        "number": "6",
        "name": "GND",
        "type": "power_in",
        "description": "Power ground; the exposed pad on the package underside must be soldered to the PCB ground."
      },
      {
        "number": "7",
        "name": "SENSE",
        "type": "input",
        "description": "External reference input; connecting it to VDD selects the internal reference with a +/-0.75V input range, while an external reference of 1.2V to 1.3V gives a +/-0.6*VSENSE input range."
      },
      {
        "number": "8",
        "name": "VREF",
        "type": "power_in",
        "description": "Reference voltage output, nominally 1.25V, bypassed to ground with a 2.2uF ceramic capacitor."
      },
      {
        "number": "9",
        "name": "GND",
        "type": "power_in",
        "description": "Power ground; the exposed pad on the package underside must be soldered to the PCB ground."
      },
      {
        "number": "10",
        "name": "VCM",
        "type": "output",
        "description": "Common-mode bias output, nominally 0.435*VDD, used to set the common-mode bias of the analog inputs and bypassed to ground with a 0.1uF ceramic capacitor."
      },
      {
        "number": "11",
        "name": "GND",
        "type": "power_in",
        "description": "Power ground; the exposed pad on the package underside must be soldered to the PCB ground."
      },
      {
        "number": "12",
        "name": "VinB-",
        "type": "input",
        "description": "Channel B differential analog input negative; the differential input voltage should be kept within 1.5V and the two inputs should be 180 degrees out of phase."
      },
      {
        "number": "13",
        "name": "VinB+",
        "type": "input",
        "description": "Channel B differential analog input positive; the differential input voltage should be kept within 1.5V and the two inputs should be 180 degrees out of phase."
      },
      {
        "number": "14",
        "name": "GND",
        "type": "power_in",
        "description": "Power ground; the exposed pad on the package underside must be soldered to the PCB ground."
      },
      {
        "number": "15",
        "name": "VDD",
        "type": "power_in",
        "description": "1.8V analog supply, bypassed to ground with 0.1uF ceramic capacitor; pins 15, 16 and 17 may share one bypass capacitor."
      },
      {
        "number": "16",
        "name": "VDD",
        "type": "power_in",
        "description": "1.8V analog supply, bypassed to ground with 0.1uF ceramic capacitor; may share the bypass capacitor with pins 15 and 17."
      },
      {
        "number": "17",
        "name": "VDD",
        "type": "power_in",
        "description": "1.8V analog supply, bypassed to ground with 0.1uF ceramic capacitor; may share the bypass capacitor with pins 15 and 16."
      },
      {
        "number": "18",
        "name": "GND",
        "type": "power_in",
        "description": "Power ground; the exposed pad on the package underside must be soldered to the PCB ground."
      },
      {
        "number": "19",
        "name": "CLK+",
        "type": "input",
        "description": "Differential clock input positive; conversion starts on the rising edge of the clock."
      },
      {
        "number": "20",
        "name": "CLK-",
        "type": "input",
        "description": "Differential clock input negative; conversion starts on the falling edge of the clock."
      },
      {
        "number": "21",
        "name": "GND",
        "type": "power_in",
        "description": "Power ground; the exposed pad on the package underside must be soldered to the PCB ground."
      },
      {
        "number": "22",
        "name": "OF-",
        "type": "output",
        "description": "Overflow/underflow LVDS output, negative leg; OF+ is high when an overflow or underflow occurs, and channel A and B overflow flags are multiplexed onto this pair."
      },
      {
        "number": "23",
        "name": "OF+",
        "type": "output",
        "description": "Overflow/underflow LVDS output, positive leg; high when an overflow or underflow occurs, and channel A and B overflow flags are multiplexed onto this pair."
      },
      {
        "number": "24",
        "name": "DB0_1-",
        "type": "output",
        "description": "Channel B DDR LVDS output negative leg carrying bit D0 while CLKOUT+ is low and bit D1 while CLKOUT+ is high."
      },
      {
        "number": "25",
        "name": "DB0_1+",
        "type": "output",
        "description": "Channel B DDR LVDS output positive leg carrying bit D0 while CLKOUT+ is low and bit D1 while CLKOUT+ is high."
      },
      {
        "number": "26",
        "name": "DB2_3-",
        "type": "output",
        "description": "Channel B DDR LVDS output negative leg carrying bit D2 while CLKOUT+ is low and bit D3 while CLKOUT+ is high."
      },
      {
        "number": "27",
        "name": "DB2_3+",
        "type": "output",
        "description": "Channel B DDR LVDS output positive leg carrying bit D2 while CLKOUT+ is low and bit D3 while CLKOUT+ is high."
      },
      {
        "number": "28",
        "name": "DB4_5-",
        "type": "output",
        "description": "Channel B DDR LVDS output negative leg carrying bit D4 while CLKOUT+ is low and bit D5 while CLKOUT+ is high."
      },
      {
        "number": "29",
        "name": "DB4_5+",
        "type": "output",
        "description": "Channel B DDR LVDS output positive leg carrying bit D4 while CLKOUT+ is low and bit D5 while CLKOUT+ is high."
      },
      {
        "number": "30",
        "name": "DB6_7-",
        "type": "output",
        "description": "Channel B DDR LVDS output negative leg carrying bit D6 while CLKOUT+ is low and bit D7 while CLKOUT+ is high."
      },
      {
        "number": "31",
        "name": "DB6_7+",
        "type": "output",
        "description": "Channel B DDR LVDS output positive leg carrying bit D6 while CLKOUT+ is low and bit D7 while CLKOUT+ is high."
      },
      {
        "number": "32",
        "name": "DVDD",
        "type": "power_in",
        "description": "1.8V supply for the digital output drivers, bypassed to ground with a separate 0.1uF ceramic capacitor per pin."
      },
      {
        "number": "33",
        "name": "DGND",
        "type": "power_in",
        "description": "Ground for the digital output drivers."
      },
      {
        "number": "34",
        "name": "DB8_9-",
        "type": "output",
        "description": "Channel B DDR LVDS output negative leg carrying bit D8 while CLKOUT+ is low and bit D9 while CLKOUT+ is high."
      },
      {
        "number": "35",
        "name": "DB8_9+",
        "type": "output",
        "description": "Channel B DDR LVDS output positive leg carrying bit D8 while CLKOUT+ is low and bit D9 while CLKOUT+ is high."
      },
      {
        "number": "36",
        "name": "DB10_11-",
        "type": "output",
        "description": "Channel B DDR LVDS output negative leg carrying bit D10 while CLKOUT+ is low and bit D11 while CLKOUT+ is high."
      },
      {
        "number": "37",
        "name": "DB10_11+",
        "type": "output",
        "description": "Channel B DDR LVDS output positive leg carrying bit D10 while CLKOUT+ is low and bit D11 while CLKOUT+ is high."
      },
      {
        "number": "38",
        "name": "DB12_13-",
        "type": "output",
        "description": "Channel B DDR LVDS output negative leg carrying bit D12 while CLKOUT+ is low and bit D13 while CLKOUT+ is high."
      },
      {
        "number": "39",
        "name": "DB12_13+",
        "type": "output",
        "description": "Channel B DDR LVDS output positive leg carrying bit D12 while CLKOUT+ is low and bit D13 while CLKOUT+ is high."
      },
      {
        "number": "40",
        "name": "CLKOUT-",
        "type": "output",
        "description": "Data output clock LVDS negative leg, which normally transitions together with the data outputs; its phase can be delayed relative to the data through the timing register."
      },
      {
        "number": "41",
        "name": "CLKOUT+",
        "type": "output",
        "description": "Data output clock LVDS positive leg, which normally transitions together with the data outputs; its phase can be delayed relative to the data through the timing register."
      },
      {
        "number": "42",
        "name": "DA0_1-",
        "type": "output",
        "description": "Channel A DDR LVDS output negative leg carrying bit D0 while CLKOUT+ is low and bit D1 while CLKOUT+ is high."
      },
      {
        "number": "43",
        "name": "DA0_1+",
        "type": "output",
        "description": "Channel A DDR LVDS output positive leg carrying bit D0 while CLKOUT+ is low and bit D1 while CLKOUT+ is high."
      },
      {
        "number": "44",
        "name": "DA2_3-",
        "type": "output",
        "description": "Channel A DDR LVDS output negative leg carrying bit D2 while CLKOUT+ is low and bit D3 while CLKOUT+ is high."
      },
      {
        "number": "45",
        "name": "DA2_3+",
        "type": "output",
        "description": "Channel A DDR LVDS output positive leg carrying bit D2 while CLKOUT+ is low and bit D3 while CLKOUT+ is high."
      },
      {
        "number": "46",
        "name": "DA4_5-",
        "type": "output",
        "description": "Channel A DDR LVDS output negative leg carrying bit D4 while CLKOUT+ is low and bit D5 while CLKOUT+ is high."
      },
      {
        "number": "47",
        "name": "DA4_5+",
        "type": "output",
        "description": "Channel A DDR LVDS output positive leg carrying bit D4 while CLKOUT+ is low and bit D5 while CLKOUT+ is high."
      },
      {
        "number": "48",
        "name": "DGND",
        "type": "power_in",
        "description": "Ground for the digital output drivers."
      },
      {
        "number": "49",
        "name": "DVDD",
        "type": "power_in",
        "description": "1.8V supply for the digital output drivers, bypassed to ground with a separate 0.1uF ceramic capacitor per pin."
      },
      {
        "number": "50",
        "name": "DA6_7-",
        "type": "output",
        "description": "Channel A DDR LVDS output negative leg carrying bit D6 while CLKOUT+ is low and bit D7 while CLKOUT+ is high."
      },
      {
        "number": "51",
        "name": "DA6_7+",
        "type": "output",
        "description": "Channel A DDR LVDS output positive leg carrying bit D6 while CLKOUT+ is low and bit D7 while CLKOUT+ is high."
      },
      {
        "number": "52",
        "name": "DA8_9-",
        "type": "output",
        "description": "Channel A DDR LVDS output negative leg carrying bit D8 while CLKOUT+ is low and bit D9 while CLKOUT+ is high."
      },
      {
        "number": "53",
        "name": "DA8_9+",
        "type": "output",
        "description": "Channel A DDR LVDS output positive leg carrying bit D8 while CLKOUT+ is low and bit D9 while CLKOUT+ is high."
      },
      {
        "number": "54",
        "name": "DA10_11-",
        "type": "output",
        "description": "Channel A DDR LVDS output negative leg carrying bit D10 while CLKOUT+ is low and bit D11 while CLKOUT+ is high."
      },
      {
        "number": "55",
        "name": "DA10_11+",
        "type": "output",
        "description": "Channel A DDR LVDS output positive leg carrying bit D10 while CLKOUT+ is low and bit D11 while CLKOUT+ is high."
      },
      {
        "number": "56",
        "name": "DA12_13-",
        "type": "output",
        "description": "Channel A DDR LVDS output negative leg carrying bit D12 while CLKOUT+ is low and bit D13 while CLKOUT+ is high."
      },
      {
        "number": "57",
        "name": "DA12_13+",
        "type": "output",
        "description": "Channel A DDR LVDS output positive leg carrying bit D12 while CLKOUT+ is low and bit D13 while CLKOUT+ is high."
      },
      {
        "number": "58",
        "name": "GND",
        "type": "power_in",
        "description": "Power ground; the exposed pad on the package underside must be soldered to the PCB ground."
      },
      {
        "number": "59",
        "name": "SPI_MISO",
        "type": "output",
        "description": "SPI data readback output in serial mode (MODE=0), open-drain and requiring a 2K pull-up to the 1.8V to 3.3V SPI supply when registers are read back; no function in parallel mode."
      },
      {
        "number": "60",
        "name": "SPI_MOSI",
        "type": "input",
        "description": "SPI data input in serial mode (MODE=0); in parallel mode (MODE=VDD) it selects LVDS output current, 3.5mA when low and 1.75mA when high at 1.8V to 3.3V logic levels."
      },
      {
        "number": "61",
        "name": "SPI_SCLK",
        "type": "input",
        "description": "SPI clock input in serial mode (MODE=0); in parallel mode (MODE=VDD) it enables sleep mode when high at 1.8V to 3.3V logic levels."
      },
      {
        "number": "62",
        "name": "SPI_CS",
        "type": "input",
        "description": "SPI chip select in serial mode (MODE=0); in parallel mode (MODE=VDD) it enables the clock duty cycle stabilizer when high at 1.8V to 3.3V logic levels."
      },
      {
        "number": "63",
        "name": "MODE",
        "type": "input",
        "description": "Serial/parallel interface mode select; connect directly to GND for SPI mode or to VDD for parallel GPIO mode and do not drive it with a logic signal."
      },
      {
        "number": "64",
        "name": "VDD",
        "type": "power_in",
        "description": "1.8V analog supply, bypassed to ground with 0.1uF ceramic capacitor; may share the bypass capacitor with pins 1 and 2."
      },
      {
        "number": "65",
        "name": "EP",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The ordering table (page 13) lists ZGAD250D14 as QFN64 DDR LVDS, matching the QFN-64 (9x9) hint. Pin"
        ],
        "pages_sent": 19,
        "cost_usd": 0.0598,
        "at": "2026-11-02T17:04:08"
      },
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/fe7f64d7964415288aacae79074c1bdf.pdf",
        "pages": 19,
        "sha256": "60a81de455573fc7",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 65,
        "described": 65,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
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        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "dce07a86ec3fe3ca87eebdff13827f55e036ced5518fee01f85cec4a3f56366d",
        "checked": "2026-11-02",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
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        "sha256": "c8e6ed4e7910f33de920bead38f2c83b6a43db0fa97885b37b3aed85dfbe9903",
        "checked": "2026-11-02",
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  }
}