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ZGAD125D14

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Zynalog Analog To Digital Converters (ADCs), QFN-64(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionzgad125d14factory-2.0.0extractor-text

Verified ZGAD125D14

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier lcsc, 65 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ZGAD125D14 · QFN-64(9x9) · 65 pins
  • ✓copper: 65 copper pads, none touching another net
  • ✓datasheet: all 65 pin names found in the 19-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-qiggf28w/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 65 pins = 65 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 65 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ zgad125d14.kicad_sym✓ zgad125d14.kicad_mod✓ zgad125d14.step
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ZGAD125D14

Zynalog · Analog To Digital Converters (ADCs) · QFN-64(9x9)

ZGAD125D14 from Zynalog, in a QFN-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in 1.8V analog supply, bypassed to ground with a 0.1uF ceramic capacitor (pins 1, 2 and 64 may share one capacitor).
2 VDD power_in 1.8V analog supply, bypassed to ground with a 0.1uF ceramic capacitor (pins 1, 2 and 64 may share one capacitor).
3 GND power_in Power ground; the exposed pad on the underside must be soldered to the PCB ground.
4 VinA+ input Channel A positive differential analog input; the differential input voltage should stay within 1.5V.
5 VinA- input Channel A negative differential analog input, driven 180 degrees out of phase with VinA+.
6 GND power_in Power ground.
7 SENSE input External reference input: tie to VDD for the internal reference (+/-0.75V input range), or to an external reference between 1.2V and 1.3V (+/-0.6*VSENSE input range).
8 VREF power_in Reference voltage output, nominally 1.25V, bypassed to ground with a 2.2uF ceramic capacitor.
9 GND power_in Power ground.
10 VCM output Common-mode bias output, nominally 0.435*VDD, used to set the analog input common mode and bypassed to ground with a 0.1uF ceramic capacitor.
11 GND power_in Power ground.
12 VinB- input Channel B negative differential analog input, driven 180 degrees out of phase with VinB+.
13 VinB+ input Channel B positive differential analog input; the differential input voltage should stay within 1.5V.
14 GND power_in Power ground.
15 VDD power_in 1.8V analog supply; pins 15, 16 and 17 may share one bypass capacitor.
16 VDD power_in 1.8V analog supply; pins 15, 16 and 17 may share one bypass capacitor.
17 VDD power_in 1.8V analog supply; pins 15, 16 and 17 may share one bypass capacitor.
18 GND power_in Power ground.
19 CLK+ input Differential clock input; conversion starts on the rising edge of CLK+.
20 CLK- input Differential clock input; conversion starts on the falling edge of CLK+ (complement input).
21 GND power_in Power ground.
22 OF- output Overflow/underflow digital output, multiplexed for channels A and B; OF+ is high when an overflow or underflow occurs.
23 OF+ output Overflow/underflow digital output, multiplexed for channels A and B; OF+ is high when an overflow or underflow occurs.
24 DB0_1- output Channel B DDR LVDS output carrying D0 while CLKOUT+ is low and D1 while CLKOUT+ is high.
25 DB0_1+ output Channel B DDR LVDS output carrying D0 while CLKOUT+ is low and D1 while CLKOUT+ is high.
26 DB2_3- output Channel B DDR LVDS output carrying D2 while CLKOUT+ is low and D3 while CLKOUT+ is high.
27 DB2_3+ output Channel B DDR LVDS output carrying D2 while CLKOUT+ is low and D3 while CLKOUT+ is high.
28 DB4_5- output Channel B DDR LVDS output carrying D4 while CLKOUT+ is low and D5 while CLKOUT+ is high.
29 DB4_5+ output Channel B DDR LVDS output carrying D4 while CLKOUT+ is low and D5 while CLKOUT+ is high.
30 DB6_7- output Channel B DDR LVDS output carrying D6 while CLKOUT+ is low and D7 while CLKOUT+ is high.
31 DB6_7+ output Channel B DDR LVDS output carrying D6 while CLKOUT+ is low and D7 while CLKOUT+ is high.
32 DVDD power_in 1.8V supply for the digital output drivers; each pin is bypassed to ground with a separate 0.1uF ceramic capacitor.
33 DGND power_in Ground for the digital output drivers.
34 DB8_9- output Channel B DDR LVDS output carrying D8 while CLKOUT+ is low and D9 while CLKOUT+ is high.
35 DB8_9+ output Channel B DDR LVDS output carrying D8 while CLKOUT+ is low and D9 while CLKOUT+ is high.
36 DB10_11- output Channel B DDR LVDS output carrying D10 while CLKOUT+ is low and D11 while CLKOUT+ is high.
37 DB10_11+ output Channel B DDR LVDS output carrying D10 while CLKOUT+ is low and D11 while CLKOUT+ is high.
38 DB12_13- output Channel B DDR LVDS output carrying D12 while CLKOUT+ is low and D13 while CLKOUT+ is high.
39 DB12_13+ output Channel B DDR LVDS output carrying D12 while CLKOUT+ is low and D13 while CLKOUT+ is high.
40 CLKOUT- output LVDS data output clock; the data normally transitions on the edges of CLKOUT+, and CLKOUT+ can be phase-shifted by programming the mode register.
41 CLKOUT+ output LVDS data output clock; the data normally transitions on the edges of CLKOUT+, and CLKOUT+ can be phase-shifted by programming the mode register.
42 DA0_1- output Channel A DDR LVDS output carrying D0 while CLKOUT+ is low and D1 while CLKOUT+ is high.
43 DA0_1+ output Channel A DDR LVDS output carrying D0 while CLKOUT+ is low and D1 while CLKOUT+ is high.
44 DA2_3- output Channel A DDR LVDS output carrying D2 while CLKOUT+ is low and D3 while CLKOUT+ is high.
45 DA2_3+ output Channel A DDR LVDS output carrying D2 while CLKOUT+ is low and D3 while CLKOUT+ is high.
46 DA4_5- output Channel A DDR LVDS output carrying D4 while CLKOUT+ is low and D5 while CLKOUT+ is high.
47 DA4_5+ output Channel A DDR LVDS output carrying D4 while CLKOUT+ is low and D5 while CLKOUT+ is high.
48 DGND power_in Ground for the digital output drivers.
49 DVDD power_in 1.8V supply for the digital output drivers; each pin is bypassed to ground with a separate 0.1uF ceramic capacitor.
50 DA6_7- output Channel A DDR LVDS output carrying D6 while CLKOUT+ is low and D7 while CLKOUT+ is high.
51 DA6_7+ output Channel A DDR LVDS output carrying D6 while CLKOUT+ is low and D7 while CLKOUT+ is high.
52 DA8_9- output Channel A DDR LVDS output carrying D8 while CLKOUT+ is low and D9 while CLKOUT+ is high.
53 DA8_9+ output Channel A DDR LVDS output carrying D8 while CLKOUT+ is low and D9 while CLKOUT+ is high.
54 DA10_11- output Channel A DDR LVDS output carrying D10 while CLKOUT+ is low and D11 while CLKOUT+ is high.
55 DA10_11+ output Channel A DDR LVDS output carrying D10 while CLKOUT+ is low and D11 while CLKOUT+ is high.
56 DA12_13- output Channel A DDR LVDS output carrying D12 while CLKOUT+ is low and D13 while CLKOUT+ is high.
57 DA12_13+ output Channel A DDR LVDS output carrying D12 while CLKOUT+ is low and D13 while CLKOUT+ is high.
58 GND power_in Power ground.
59 SPI_MISO output SPI data readback output in serial mode; it is open-drain and needs a 2K pull-up to the 1.8V to 3.3V SPI supply when read back, and has no function in parallel mode.
60 SPI_MOSI input SPI data input in serial mode (MODE=0); in parallel mode it selects LVDS drive current, 0 (GND) for 3.5mA and 1 for 1.75mA with 1.8V to 3.3V logic.
61 SPI_SCLK input SPI clock in serial mode (MODE=0); in parallel mode a logic 1 (1.8V to 3.3V) puts the device into sleep (AC power down) mode.
62 SPI_CS input SPI chip select in serial mode (MODE=0); in parallel mode a logic 1 (1.8V to 3.3V) enables the clock duty cycle stabilizer.
63 MODE input Serial/parallel mode select: connect directly to GND for SPI mode or to VDD for parallel GPIO mode, and do not drive it with a logic signal.
64 VDD power_in 1.8V analog supply; pins 1, 2 and 64 may share one bypass capacitor.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Zynalog
Package QFN-64(9x9)
Category ADC/DAC/Data Conversion
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
模拟电源输入电压 VDD 1.7 1.8 1.9 V 4
数字电源输入电压 DVDD 1.7 1.8 1.9 V 4
最大输入电压范围 VDD,DVDD -0.3 2 V 6
最大输入模拟电压范围 Analog Vin -0.3 V 最大值 VDD+0.2 6
SPI/GPIO 最大数字电压范围 SPI 3.9 V 下限 VDD 6
LVDS 输出最大数字电压范围 Data Output -0.3 V 最大值 DVDD+0.2 6
工作温度 -40 85 °C 6
储存温度 -65 150 °C 6
积分非线性 INL -2 1 2 LSB 4
微分非线性 DNL -0.6 0.35 0.6 LSB 4
偏置误差 Offset Error -13 5 13 mV 4
增益误差 Gain Error -4 1 2.2 %FS 4
数字输出差分电压 (3.5mA 模式下) V_OD 247 350 454 mV 3.5mA 模式 4
数字输出差分电压 (1.75mA 模式下) V_OD 125 175 250 mV 1.75mA 模式 4
数字输出共模电压 V_OS 1.125 1.25 1.375 V 4
时钟输入高保持时间 tH 3.8 4 ns VDD=1.8V, DVDD=1.8V, fS=125MHz 10
时钟输入低保持时间 tL 3.8 4 ns VDD=1.8V, DVDD=1.8V, fS=125MHz 10
时钟输入和时钟输出的延迟 tC 1.3 1.6 2 ns VDD=1.8V, DVDD=1.8V, fS=125MHz 10
时钟输入和数据输出的延迟 tD 1.7 2 2.3 ns VDD=1.8V, DVDD=1.8V, fS=125MHz 10
时钟输出和数据输出的差值 (tC − tD) tSKEW 0.1 0.2 0.55 ns VDD=1.8V, DVDD=1.8V, fS=125MHz 10
模拟电源输入电流 I_VDD 184 186 mA 4
数字电源输入电流 I_DVDD 48 mA 4
1.75mA LVDS 输出时功耗 (双通道同时开启) P_1.75 370 mW 双通道同时开启 4
3.5mA LVDS 输出时功耗 (双通道同时开启) P_3.5 418 mW 双通道同时开启 4
低功耗模式 P_lowpower 135 mW 4
睡眠模式 P_sleep 0.65 mW 4
信噪比 SNR 70 dB 4
无杂散动态范围 SFDR 90 dB 4
时钟输入和数据采集的延迟 tAP 0.5 ns 数据位延迟 6 个周期 10
CS 拉低到时钟 CLK 的建立时间 tS 5 ns SPI_MISO 上拉电阻 2KΩ 15
数据建立时间 tDS 5 ns SPI_MISO 上拉电阻 2KΩ 15
数据保持时间 tDH 5 ns SPI_MISO 上拉电阻 2KΩ 15
时钟 CLK 到数据输出的延迟 tDO 125 ns SPI_MISO 上拉电阻 2KΩ 15
时钟周期 (写入) tSCK 40 ns 写入; SPI_MISO 上拉电阻 2KΩ 15
时钟周期 (读回) tSCK 250 ns 读回; SPI_MISO 上拉电阻 2KΩ 15
时钟 CLK 到 CS 拉高的保持时间 tH 5 ns SPI_MISO 上拉电阻 2KΩ 15

CAD (KiCad official)

  • Symbol: ZGAD125D14
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: QFN-64(9x9) (KiCad packages3D, STEP)
  • 3D model files: zgad125d14-etched.step / zgad125d14-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); zgad125d14.step / zgad125d14.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Zynalog datasheet (19 pp, sha256 636e51e2f0d18770, retrieved 2026-11-02, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF