component

ZED-F9P-04B

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by adom

u-blox ZED-F9P-04B multi-band (L1/L2) high precision RTK GNSS module, 17.0 x 22.0 x 2.4 mm LGA-54 with 48 central ground pads. KiCad symbol, footprint, Fusion library and 3D.

componentgnssgpsrtkmulti-bandmodulelgau-bloxzed-f9pzed-f9p-04b
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Generated by adom_component_libgen · KiCad file format 20241229
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docs models.json in adom/models@1 tool format with thumbnails · John Lauer 2d ago
provenance zed-f9p-04b: component page files (3/4) · John Lauer 2d ago
viewers zed-f9p-04b: component page files (3/4) · John Lauer 2d ago
LICENSE zed-f9p-04b: component page files (3/4) · John Lauer 2d ago
models.json models.json in adom/models@1 tool format with thumbnails · John Lauer 2d ago
page.json page.json: list model thumbnails · John Lauer 2d ago
README.md zed-f9p-04b: component page files (3/4) · John Lauer 2d ago
zed-f9p-04b-etched.glb zed-f9p-04b: component page files (2/4) · John Lauer 2d ago
zed-f9p-04b-etched.step zed-f9p-04b: component page files (1/4) · John Lauer 2d ago
zed-f9p-04b-hero.glb zed-f9p-04b: component page files (2/4) · John Lauer 2d ago
zed-f9p-04b-hero.overlay.json zed-f9p-04b: component page files (3/4) · John Lauer 2d ago
zed-f9p-04b.glb zed-f9p-04b: component page files (3/4) · John Lauer 2d ago
zed-f9p-04b.kicad_mod zed-f9p-04b: component page files (3/4) · John Lauer 2d ago
zed-f9p-04b.kicad_sym zed-f9p-04b: component page files (3/4) · John Lauer 2d ago
zed-f9p-04b.lbr zed-f9p-04b: component page files (3/4) · John Lauer 2d ago
zed-f9p-04b.step zed-f9p-04b: component page files (2/4) · John Lauer 2d ago

ZED-F9P-04B

u-blox · GNSS receiver modules (multi-band RTK) · LGA-54 (54 edge pads + 48 central GND pads), 22.0 x 17.0 x 2.4 mm

u-blox ZED-F9P-04B multi-band (L1/L2) high precision RTK GNSS module, 17.0 x 22.0 x 2.4 mm LGA-54 with 48 central ground pads.

Key specifications

Parameter Value Source
Receiver u-blox F9, multi-band, RTK and PPP-RTK (SPARTN, CLAS) p.4
Signals GPS/QZSS L1C/A + L2C, GLONASS L1OF + L2OF, Galileo E1-B/C + E5b, BeiDou B1I + B2I Table 7, p.6-7
Horizontal accuracy (CEP) PVT 1.5 m, SBAS 1.0 m, RTK 0.01 m + 1 ppm Table 3, p.5
RTK convergence < 10 s (multi-GNSS) Table 2, p.5
Max navigation rate RTK up to 20 Hz (GPS only), 7 Hz (4 GNSS) Table 1, p.4
Time pulse accuracy 30 ns RMS Table 1, p.4
Supply VCC 2.7 V to 3.6 V (3.0 V typ) Table 15, p.14
Backup supply V_BCKP 1.65 V to 3.6 V, 45 uA typ Table 15, p.14
Current (GPS+GLO, acquisition / tracking) 90 mA / 85 mA typ, 130 mA peak Table 16, p.15
Interfaces 2 x UART, SPI, I2C, USB 2.0 (full speed) sec. 5, p.16-19
Operating temperature -40 C to +85 C Table 15, p.15
Size 17.0 x 22.0 x 2.4 mm sec. 6, p.20
Firmware as shipped HPG 1.32 (type number ZED-F9P-04B-01) sec. 8.3, p.23

Pinout

Pin Name Type Function
1 GND power_in Ground
2 RF_IN input RF input (GNSS antenna feed 50 ohm)
3 GND power_in Ground
4 ANT_DETECT input Active antenna detect - default active high
5 ANT_OFF output External LNA disable - default active high
6 ANT_SHORT_N input Active antenna short detect - default active low
7 VCC_RF power_out Voltage for external LNA
8 Reserved no_connect Reserved - leave open
9 Reserved no_connect Reserved - leave open
10 Reserved no_connect Reserved - leave open
11 Reserved no_connect Reserved - leave open
12 GND power_in Ground
13 Reserved no_connect Reserved - leave open
14 GND power_in Ground
15 Reserved no_connect Reserved - leave open
16 Reserved no_connect Reserved - leave open
17 Reserved no_connect Reserved - leave open
18 Reserved no_connect Reserved - leave open
19 GEOFENCE_STAT output Geofence status, user defined
20 RTK_STAT output RTK status: 0 = RTK fixed, blinking = receiving/using corrections, 1 = no corrections
21 Reserved no_connect Reserved - leave open
22 Reserved no_connect Reserved - leave open
23 Reserved no_connect Reserved - leave open
24 Reserved no_connect Reserved - leave open
25 Reserved no_connect Reserved - leave open
26 RXD2 input Correction UART input
27 TXD2 output Correction UART output
28 Reserved no_connect Reserved - leave open
29 Reserved no_connect Reserved - leave open
30 Reserved no_connect Reserved - leave open
31 Reserved no_connect Reserved - leave open
32 GND power_in Ground
33 VCC power_in Voltage supply
34 VCC power_in Voltage supply
35 Reserved no_connect Reserved - leave open
36 V_BCKP power_in Backup supply voltage
37 GND power_in Ground
38 V_USB power_in USB supply
39 USB_DM bidirectional USB data
40 USB_DP bidirectional USB data
41 GND power_in Ground
42 TXD/SPI_SDO output Host UART output if D_SEL = 1 (or open); SPI_SDO if D_SEL = 0
43 RXD/SPI_SDI input Host UART input if D_SEL = 1 (or open); SPI_SDI if D_SEL = 0
44 SDA/SPI_CS_N bidirectional I2C data if D_SEL = 1 (or open); SPI chip select if D_SEL = 0
45 SCL/SPI_CLK bidirectional I2C clock if D_SEL = 1 (or open); SPI clock if D_SEL = 0
46 TX_READY output TX buffer full and ready for TX of data
47 D_SEL input Interface select for pins 42-45 (open/1 = UART+I2C, 0 = SPI); input pull-up
48 GND power_in Ground
49 RESET_N input RESET_N (input pull-up)
50 SAFEBOOT_N input SAFEBOOT_N (for future service, updates and reconfiguration; leave OPEN)
51 EXTINT input External interrupt pin
52 Reserved no_connect Reserved - leave open
53 TIMEPULSE output Time pulse
54 Reserved no_connect Reserved - leave open
55 GND power_in Central ground pads (48 x 1.1 mm square, unnumbered in u-blox docs; numbered 55 here)

Source: UBX-21044850 R05 sec 3.1 Fig 3 + Table 12 (pp.11-13); pin states Table 13 (p.13).

Footprint and pin 1

Pin 1 is the left-most pad of the bottom row in the top view (as placed on the PCB); pins 1 to 14 run left to right along the bottom edge and the numbering continues counter-clockwise (15 to 27 up the right side, 28 to 41 along the top, 42 to 54 down the left side). Pin 1 sits next to the 0.70 mm square pin-1 indicator copper that the u-blox land pattern places outside the corner (Integration manual Fig. 49 / Table 44). The 3D model carries a disc over the same corner as a visual aid; it is not a u-blox marking.

Land pattern source: UBX-18010802 R16 sec 4.7.3.1 Fig 49 + Table 44 (p.101) copper; sec 4.7.3.2 Fig 50 + Table 45 (p.102) paste.

Dimension Value (mm)
edge pad copper 1.50 x 0.80
edge pitch 1.1
side column centre x 9.95
top bottom row centre y 7.45
side pad y +-0.55..+-6.60
row pad x +-0.55..+-7.15
centre gnd pad 1.10 sq, pitch 2.10, cols +-1.05/3.15/5.25/7.35, rows +-1.05/3.15/5.25
pin1 indicator 0.70 sq at (-8.35, +7.75) [P=1.20 from first bottom pad, Q=0.30 below row]
paste edge 1.55 x 0.75 centred at 10.00 / 7.50
paste centre 1.05 sq
courtyard keep-out area 23.0 x 17.4

3D models

No manufacturer 3D model was available, so the model is AI-created: built by Adom from the datasheet drawing (UBX-21044850 R05 sec 6 Fig 6 + Table 24 (pp.20-21)). It is a simplified body (substrate, shield or lid, and the contact pads), Z-up and seated on z = 0, centred on the footprint origin.

Simplifications and assumptions: No u-blox STEP found (web search 2026-10-17); simplified model; Substrate/shield split and shield inset not dimensioned by u-blox; Pin-1 disc on top is a visual aid, not a u-blox marking; De-panel residual tabs (L 0-0.3 mm) not modelled.

File What it is
zed-f9p-04b.step / zed-f9p-04b.glb Plain model
zed-f9p-04b-etched.step / zed-f9p-04b-etched.glb The same model with the MPN as a virtual laser mark (top face, adom-aiflow-etch, gate PASS). This is the board/library model.
zed-f9p-04b-hero.glb The page's 3D view: the marked model plus teal dashed pad outlines, silkscreen with pin 1 and signal names (adom-hero 1.4). Not for boards.

The MPN mark is an identification aid added by Adom, not a claim about the manufacturer's real marking.

Sourcing

Distributor Part number
Mouser 377-ZED-F9P-04B
DigiKey 672-ZED-F9P-04BTR-ND
LCSC C5120257

Snapshot 2026-10-17 (adom-parts-search): Mouser 377-ZED-F9P-04B: 4,139 in stock, USD 131.74 (1 pc), USD 116.56 (100). DigiKey 672-ZED-F9P-04BTR-ND: 6,522 in stock, USD 127.42. LCSC C5120257: 17 in stock.

Manufacturer and resources

Manufacturer documents are linked, not copied: their terms do not allow redistribution.

Provenance

File Classification Source
zed-f9p-04b.kicad_sym source-derived UBX-21044850 R05 sec 3.1 Fig 3 + Table 12 (pp.11-13); pin states Table 13 (p.13)
zed-f9p-04b.kicad_mod source-derived UBX-18010802 R16 sec 4.7.3.1 Fig 49 + Table 44 (p.101) copper; sec 4.7.3.2 Fig 50 + Table 45 (p.102) paste
zed-f9p-04b.step AI-created UBX-21044850 R05 sec 6 Fig 6 + Table 24 (pp.20-21)
zed-f9p-04b-etched.step derived (virtual MPN mark added) zed-f9p-04b.step
zed-f9p-04b.glb derived (format conversion) zed-f9p-04b.step
zed-f9p-04b-etched.glb derived (format conversion) zed-f9p-04b-etched.step
zed-f9p-04b-hero.glb derived (annotated presentation model, not for board use) zed-f9p-04b-etched.glb, zed-f9p-04b.kicad_mod, page.json component.pins
zed-f9p-04b.lbr derived zed-f9p-04b.kicad_sym, zed-f9p-04b.kicad_mod

Every file's SHA-256, the source documents with their hashes and retrieval dates, the dimensions used and the assumptions are in provenance/provenance.json. The MPN mark plan and gate result are in provenance/.

Found a wrong pin, pad or dimension? Open an issue on this page with the file name and hash, the disputed value, the source page and a screenshot.

License

Adom-authored files: CC BY-SA 4.0. See LICENSE.