component

ZD25WQ16CTIGT

Public Made by Adom

by adom

Zetta NOR FLASH, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs zd25wq16ctigt: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 4d ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
package.json Publish 0.2.0 · Ray 1mo ago
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
page.json Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout") · Ray 11d ago
README.md zd25wq16ctigt: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 17d ago
zd25wq16ctigt-etched.fit.json zd25wq16ctigt: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 4d ago
zd25wq16ctigt-etched.glb zd25wq16ctigt: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 4d ago
zd25wq16ctigt-etched.step zd25wq16ctigt: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 4d ago
zd25wq16ctigt.glb Publish 0.1.0 · Ray 1mo ago
zd25wq16ctigt.kicad_mod Publish 0.1.0 · Ray 1mo ago
zd25wq16ctigt.kicad_sym Publish 0.1.0 · Ray 1mo ago
zd25wq16ctigt.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect and oval pad as a SQUARE EAGLE smd; this carries the real pad shape across (0 -> 8 rounded pads) and stops dropping geometry drawn on KiCad User.N layers. Attributes, connects, pads and the pin-1 marker are gated against decreasing and are unchanged. · Ray 1mo ago
zd25wq16ctigt.step Publish 0.1.0 · Ray 1mo ago

ZD25WQ16CTIGT

Zetta · NOR FLASH · SOP-8

ZD25WQ16CTIGT from Zetta, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS# input Chip Select input, active low. Drives the device into active mode on falling edge and into standby (SO High-Z) on rising edge. Must be pulled high externally when the master is idle.
2 SO/IO1 bidirectional Standard SPI Serial Data Output (SO); becomes bidirectional data line IO1 in Dual/Quad SPI and QPI modes. Data is shifted out on the falling edge of SCLK in standard mode.
3 WP#/IO2 bidirectional Write Protect input (active low) when QE=0, gating Status Register writes together with SRP1/SRP0. When QE=1 the pin serves as bidirectional Quad data line IO2. Do not tie directly to VCC/GND if Quad operation may be used.
4 VSS power_in Ground reference (0 V) for the device. Connect to the system ground plane with a short, low-inductance path.
5 SI/IO0 bidirectional Standard SPI Serial Data Input (SI); becomes bidirectional data line IO0 in Dual/Quad SPI and QPI modes. Data is latched on the rising edge of SCLK in standard mode.
6 SCLK input Serial Clock input, up to 104 MHz. Supports SPI mode 0 and mode 3 (CPOL/CPHA = 0/0 or 1/1). Input data is latched on the rising edge and output data is shifted on the falling edge.
7 HOLD#/IO3 bidirectional Hold input (active low) when QE=0; pausing serial communication while CS# stays low and driving SO High-Z. When QE=1 the pin serves as bidirectional Quad data line IO3. HOLD function is disabled in Quad I/O and QPI modes.
8 VCC power_in Device power supply, 1.65 V to 3.6 V for read, program and erase. Decouple to VSS with a 100 nF ceramic capacitor placed close to the pin.

Key specifications

Parameter Value
Manufacturer Zetta
Package SOP-8
Category Memory
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • ZD25WQ16CTIGT
  • ZD25WQ16CTIGR
  • ZD25WQ16CTIGTCTEGT
  • ZD25WQ16CTIGTCTEGR
  • ZD25WQ16CTIGTCSIG
  • ZD25WQ16CTIGTCSEG
  • ZD25WQ16CTIGTCOIG
  • ZD25WQ16CTIGTCOEG
  • ZD25WQ16CTIGTCUIG
  • ZD25WQ16CTIGTCUEG
  • ZD25WQ16CTIGTCEIG
  • ZD25WQ16CTIGTCEEG

CAD (KiCad official)

  • Symbol: ZD25WQ16CTIGT
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: zd25wq16ctigt-etched.step / zd25wq16ctigt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); zd25wq16ctigt.step / zd25wq16ctigt.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
zd25wq16ctigt.step 122 KB You want the bare part, or you mark your own boards.
zd25wq16ctigt-etched.step 2.3 MB You want the part with ZD25WQ16CTIGT already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 583 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Zetta datasheet (87 pp, sha256 bfa49c113191080d, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF