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docs zd25wd20ceigr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 14d ago
viewers Strip the Cloudflare-injected script from the viewer files (edge poisoning, adom/wiki#200 class) · Colby Knox 12d ago
package.json Publish 0.2.0 · Ray 1mo ago
page.json Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout") · Ray 10d ago
README.md zd25wd20ceigr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 14d ago
zd25wd20ceigr-etched.fit.json zd25wd20ceigr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 14d ago
zd25wd20ceigr-etched.glb zd25wd20ceigr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 14d ago
zd25wd20ceigr-etched.step zd25wd20ceigr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 10d ago
zd25wd20ceigr.glb Publish 0.1.0 · Ray 1mo ago
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zd25wd20ceigr.step Publish 0.1.0 · Ray 1mo ago

ZD25WD20CEIGR

Zetta · NOR FLASH · USON-8(2x3)

ZD25WD20CEIGR from Zetta, in a USON-8(2x3). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS# input Chip Select input (active low). Drive low to select the device and enable command/data transfer; drive high to deselect and place SO in High-Z.
2 SO/IO1 bidirectional Serial Data Output in standard SPI mode; becomes bidirectional data line IO1 during Dual SPI operations (Dual Output Fast Read 3BH, Dual I/O Fast Read BBH, DREMS 92H).
3 NC unconnected No connection. May be left floating or tied to ground.
4 VSS power_in Ground reference for all supply and signal pins.
5 SI/IO0 bidirectional Serial Data Input in standard SPI mode; becomes bidirectional data line IO0 during Dual SPI operations. All commands, addresses, and data-in are shifted in MSB-first on the rising edge of SCLK.
6 SCLK input Serial Clock input. Supports SPI Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1). Input data is latched on the rising edge and output data is shifted on the falling edge. Max 104MHz single-I/O fast read.
7 NC unconnected No connection. May be left floating or tied to ground.
8 VCC power_in Power supply input, 1.65V to 3.6V. Typical currents: 1.3mA active read at 33MHz, 3.2mA active program/erase, 0.5uA standby, 0.3uA deep power-down.

Key specifications

Parameter Value
Manufacturer Zetta
Package USON-8(2x3)
Category Memory
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • ZD25WD20CEIGR
  • ZD25WD20CEIGREIGT
  • ZD25WD20CEIGREIGY
  • ZD25WD20CEIGREEGR
  • ZD25WD20CEIGRTIGR
  • ZD25WD20CEIGRTEGR
  • ZD25WD20CEIGRTIGT
  • ZD25WD20CEIGROIGR
  • ZD25WD20CEIGROEGR
  • ZD25WD20CEIGRKIGR
  • ZD25WD20CEIGRKEGR
  • ZD25WD20CEIGRJIGR
  • ZD25WD20CEIGRJEGR
  • ZD25WD20CEIGRFIGR
  • ZD25WD20CEIGRFEGR

CAD (KiCad official)

  • Symbol: ZD25WD20CEIGR
  • Footprint: Package_SON:Winbond_USON-8-1EP_3x2mm_P0.5mm_EP0.2x1.6mm
  • 3D model: USON-8(2x3) (KiCad packages3D, STEP)
  • 3D model files: zd25wd20ceigr-etched.step / zd25wd20ceigr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); zd25wd20ceigr.step / zd25wd20ceigr.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
zd25wd20ceigr.step 106 KB You want the bare part, or you mark your own boards.
zd25wd20ceigr-etched.step 2.2 MB You want the part with ZD25WD20CEIGR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 560 faces against 62 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Zetta datasheet (40 pp, sha256 114863a3cfb6032a, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF