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ZD25Q80BSIGT
Public Made by Adomby adom
Zetta NOR FLASH, SOP-8-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownZD25Q80BSIGT
Zetta · NOR FLASH · SOP-8-208mil
ZD25Q80BSIGT from Zetta, in a SOP-8-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS# | input | Chip select input. |
| 2 | SO | bidirectional | SIO1: serial data output for 1 x I/O, and serial data input/output for 4 x I/O read mode. |
| 3 | WP# | bidirectional | SIO2: active-low write protection input, and serial data input/output for 4 x I/O read mode. |
| 4 | GND | power_in | Ground of the device. |
| 5 | SI | bidirectional | SIO0: serial data input for 1 x I/O, and serial data input/output for 4 x I/O read mode. |
| 6 | SCLK | input | Serial interface clock input. |
| 7 | HOLD# | bidirectional | SIO3: pauses the device without deselecting it, and serial data input/output for 4 x I/O read mode. |
| 8 | VCC | power_in | Power supply of the device, 2.3 to 3.6V for read, erase and program. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Zetta |
| Package | SOP-8-208mil |
| Category | Memory |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | Vcc | 2.3 | 3.6 | V | Read, Erase and Program | 4 | |
| Operating temperature | -40 | 85 | °C | Industrial | 4 | ||
| Deep power down current | IDPD | 0.5 | 1.5 | uA | CS#=Vcc, all other inputs at 0V or Vcc | 17 | |
| Standby current | ISB | 12 | uA | CS#, HOLD#, WP#=VIH, all inputs at CMOS | 17 | ||
| Low power read current (03h) | ICC1 | 2.3 | 3 | mA | f=55MHz; IOUT=0mA | 17 | |
| Read current (0Bh) 85MHz | ICC2 | 2.8 | 4 | mA | f=85MHz; IOUT=0mA | 17 | |
| Read current (0Bh) 104MHz | ICC2 | 2.8 | 4.5 | mA | f=104MHz; IOUT=0mA | 17 | |
| Program current | ICC3 | 5 | 6 | mA | CS#=Vcc | 17 | |
| Erase current | ICC4 | 5 | 6 | mA | CS#=Vcc | 17 | |
| Input load current | ILI | 1 | uA | All inputs at CMOS | 17 | ||
| Output leakage | ILO | 1 | uA | All inputs at CMOS | 17 | ||
| Output low voltage | VOL | 0.2 | V | IOL=100uA | 17 | ||
| Storage temperature | -65 | 150 | °C | 16 | |||
| Operation temperature | -40 | 125 | °C | 16 | |||
| Maximum operation voltage | 4 | V | 16 | ||||
| Voltage on any pin with respect to ground | -0.6 | 4.1 | V | 16 | |||
| DC output current | 5 | mA | 16 | ||||
| Output capacitance | COUT | 8 | pF | VOUT=GND; TA=25°C, F=1MHz, Vcc=3.0V | 16 | ||
| Input capacitance | CIN | 6 | pF | VIN=GND; TA=25°C, F=1MHz, Vcc=3.0V | 16 | ||
| Clock frequency (FAST_READ etc.) | fSCLK | 104 | MHz | FAST_READ, RDSFDP, PP, SE, BE32K, BE, CE, DP, RES | 18 | ||
| Clock frequency for READ | fRSCLK | 55 | MHz | READ instructions | 18 | ||
| Clock frequency for 2READ, DREAD | fTSCLK | 104 | MHz | 2READ, DREAD instructions | 18 | ||
| Clock frequency for 4READ, QREAD | fQ | 104 | MHz | 4READ, QREAD instructions | 18 | ||
| Clock frequency for QPP | fQPP | 104 | MHz | Quad page program | 18 | ||
| Clock high time | tCH | 4.5 | ns | 18 | |||
| Clock low time | tCL | 4.5 | ns | 18 | |||
| CS# active setup time | tSLCH | 5 | ns | relative to SCLK | 18 | ||
| CS# not active hold time | tCHSL | 5 | ns | relative to SCLK | 18 | ||
| Data in setup time | tDVCH | 2 | ns | 18 | |||
| Data in hold time | tCHDX | 3 | ns | 18 | |||
| CS# active hold time | tCHSH | 5 | ns | relative to SCLK | 18 | ||
| CS# not active setup time | tSHCH | 5 | ns | relative to SCLK | 18 | ||
| CS# deselect time read to next read | tSHSL | 15 | ns | From Read to next Read | 18 | ||
| CS# deselect time write/erase/program to read status | tSHSL | 30 | ns | From Write, Erase, Program to Read Status Register | 18 | ||
| Output disable time | tSHQZ | 6 | ns | 18 | |||
| Clock low to output valid 30pF | tCLQV | 7 | ns | Loading 30pF | 18 | ||
| Clock low to output valid 15pF | tCLQV | 6 | ns | Loading 15pF | 18 | ||
| Output hold time | tCLQX | 0 | ns | 18 | |||
| HOLD# active setup time | tHLCH | 5 | ns | relative to SCLK | 18 | ||
| HOLD# active hold time | tCHHH | 5 | ns | relative to SCLK | 18 | ||
| HOLD# not active setup time | tHHCH | 5 | ns | relative to SCLK | 18 | ||
| HOLD# not active hold time | tCHHL | 5 | ns | relative to SCLK | 18 | ||
| HOLD# to output Low-Z | tHHQX | 6 | ns | 18 | |||
| HOLD# to output High-Z | tHLQZ | 6 | ns | 18 | |||
| Write protect setup time | tWHSL | 20 | ns | WRSR instruction only | 18 | ||
| Write protect hold time | tSHWL | 100 | ns | WRSR instruction only | 18 | ||
| CS# high to deep power-down mode | tDP | 3 | us | 18 | |||
| CS# high to standby mode without electronic signature read | tRES1 | 8 | us | 18 | |||
| CS# high to standby mode with electronic signature read | tRES2 | 8 | us | printed as 'Without Electronic Signature Read' | 18 | ||
| Write status register cycle time | tW | 8 | 12 | ms | 18 | ||
| Reset recovery time (erase/program except WRSR) | tReady | 70 | us | 18 | |||
| Reset recovery time (WRSR) | tReady | 8 | 12 | ms | 18 | ||
| Erase suspend latency | TESL | 30 | us | 19 | |||
| Program suspend latency | TPSL | 30 | us | 19 | |||
| Latency between program resume and next suspend | TPRS | 0.3 | us | 19 | |||
| Latency between erase resume and next suspend | TERS | 0.3 | us | 19 | |||
| Page program time | tPP | 2 | 3 | ms | up to 256 bytes | 19 | |
| Page erase time | tPE | 10 | 12 | ms | 19 | ||
| Sector erase time | tSE | 10 | 12 | ms | 19 | ||
| Block erase time 32K bytes | tBE1 | 10 | 12 | ms | 19 | ||
| Block erase time 64K bytes | tBE2 | 10 | 12 | ms | 19 | ||
| Chip erase time | tCE | 10 | 12 | ms | 19 |
CAD (KiCad official)
- Symbol:
ZD25Q80BSIGT - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8-208mil (KiCad packages3D, STEP)
- 3D model files:
zd25q80bsigt-etched.step/zd25q80bsigt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);zd25q80bsigt.step/zd25q80bsigt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Zetta datasheet (71 pp, sha256
dace24d0fb0778cc, retrieved 2026-10-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).