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YT8531SC

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by adom

Motorcomm Ethernet ICs, QFN-48(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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YT8531SC

Motorcomm · Ethernet ICs · QFN-48(6x6)

YT8531SC from Motorcomm, in a QFN-48(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVDD33 power_in Analog 3.3V power supply.
2 TRXP0 bidirectional Media-dependent interface 0 positive, 100Ω transmission line.
3 TRXN0 bidirectional Media-dependent interface 0 negative, 100Ω transmission line.
4 AVDDL power_in Analog 1.1V power supply.
5 TRXP1 bidirectional Media-dependent interface 1 positive, 100Ω transmission line.
6 TRXN1 bidirectional Media-dependent interface 1 negative, 100Ω transmission line.
7 TRXP2 bidirectional Media-dependent interface 2 positive, 100Ω transmission line.
8 TRXN2 bidirectional Media-dependent interface 2 negative, 100Ω transmission line.
9 AVDDL power_in Analog 1.1V power supply.
10 TRXP3 bidirectional Media-dependent interface 3 positive, 100Ω transmission line.
11 TRXN3 bidirectional Media-dependent interface 3 negative, 100Ω transmission line.
12 AVDD33 power_in Analog 3.3V power supply.
13 RESET_N input Hardware reset, active low, internal pull-up; requires an external pull-up resistor.
14 MDC input Management Data Clock, internal pull-down.
15 MDIO bidirectional Management data input/output, internal pull-up; pull up to 3.3V/2.5V/1.8V for the respective I/O voltage.
16 TXD3 input RGMII transmit data bit 3 from MAC to PHY, internal pull-down.
17 TXD2 input RGMII transmit data bit 2 from MAC to PHY, internal pull-down.
18 TXD1 input RGMII transmit data bit 1 from MAC to PHY, internal pull-down.
19 TXD0 input RGMII transmit data bit 0 from MAC to PHY, internal pull-down.
20 TX_CTL input RGMII transmit control signal from the MAC, internal pull-down.
21 TX_CLK input RGMII transmit reference clock, 125MHz, 25MHz, or 2.5MHz depending on speed, internal pull-down.
22 DVDDL power_in Digital 1.1V power supply.
23 RXD3/CFG_MODE2 bidirectional RGMII receive data bit 3 to MAC; latched at power-up as CFG_MODE2 operation mode configuration, internal pull-down.
24 RXD2/CFG_MODE1 bidirectional RGMII receive data bit 2 to MAC; latched at power-up as CFG_MODE1 operation mode configuration, internal pull-down.
25 RXD1/CFG_MODE0 bidirectional RGMII receive data bit 1 to MAC; latched at power-up as CFG_MODE0 operation mode configuration, internal pull-down.
26 RXD0/RXDLY bidirectional RGMII receive data bit 0 to MAC; latched at power-up as RXDLY, pull-up adds 2ns delay on RX_CLK, internal pull-up.
27 RX_CTL/PHYAD2 bidirectional RGMII receive control signal to MAC; latched at power-up as PHYAD2 PHY address bit, internal pull-down.
28 RX_CLK/PHYAD1 bidirectional RGMII continuous receive clock of 125MHz, 25MHz, or 2.5MHz; latched at power-up as PHYAD1, internal pull-down.
29 DVDD_RGMII power_in Digital RGMII I/O and MDC/MDIO power set by CFG_LDO[1:0]; external 3.3V when CFG_LDO[1:0]=00, otherwise from internal LDO; needs bulk and decoupling capacitors.
30 DVDD33 power_in 3.3V power for digital non-RGMII I/O.
31 VDD33_LX power_in 3.3V power for the switching regulator.
32 LX power_out Switch regulator 1.1V output; connect directly to an external 2.2uH power inductor.
33 Reserved bidirectional Reserved for internal use; keep floating or external pull-down, do not pull up.
34 INT_N/PME_N output Open-drain active-low interrupt (default) or power management event output selected by Ext 0xA00A bit[6]; should be pulled up to 3.3V, keep floating if unused.
35 LED0/PHYAD0 bidirectional LED0 (light = link up at 10Mbps, blinking = transmit/receive); latched at power-up as PHYAD0, internal pull-up.
36 LED1/CFG_LDO0 bidirectional LED1 (light = link up at 100Mbps, blinking = transmit/receive); latched at power-up as CFG_LDO0 RGMII I/O voltage select, internal pull-up.
37 LED2/CFG_LDO1 bidirectional LED2 (light = link up at 1000Mbps, blinking = transmit/receive); latched at power-up as CFG_LDO1 RGMII I/O voltage select, internal pull-down.
38 HSIP input SerDes differential input positive, 1.25GHz, internal 100 ohm differential termination.
39 HSIN input SerDes differential input negative, 1.25GHz, internal 100 ohm differential termination.
40 HSOP output SerDes differential output positive, 1.25GHz, internal 50 ohm termination to AVDDL.
41 HSON output SerDes differential output negative, 1.25GHz, internal 50 ohm termination to AVDDL.
42 NC unconnected No connect; keep floating or connect to GND.
43 Reserved passive Reserved; keep floating or connect to GND, must not connect to VDD or be pulled up.
44 CLKOUT output Reference clock from internal PLL or UTP/fiber recovered receive clock for Sync Ethernet; keep floating if unused by the MAC.
45 XTAL_I passive 25MHz crystal input; shorted to GND when an external oscillator drives XTAL_O, or driven by an external oscillator with XTAL_O floating.
46 XTAL_O passive 25MHz crystal output; can be driven by an external oscillator with XTAL_I shorted to GND, otherwise left floating.
47 AVDDL power_in Analog 1.1V power supply.
48 RBIAS output Bias resistor pin; an external 2.49kΩ ±1% resistor must be connected between RBIAS and GND.
49 GND power_in Ground, exposed pad.

Key specifications

Parameter Value
Manufacturer Motorcomm
Package QFN-48(6x6)
Category Communication Interface Chip/UART/485/232
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating temperature 0 70 °C YT8531SC Consumer grade 75
Reset: time from powers steady to reset release T1 10 ms 27
Reset: duration of reset signal low T2 10 ms 27
MDC Clock Period t1 80 ns 71
MDC High Time t2 32 ns 71
MDC Low Time t3 32 ns 71
MDIO to MDC Rising Setup Time (Data Input) t4 10 ns 71
MDIO to MDC Rising Hold Time (Data Input) t5 10 ns 71
MDIO Valid from MDC rising edge (Data Output) t6 0 20 ns 71
Crystal reference frequency Fref 25 MHz Parallel resonant crystal 71
Crystal frequency tolerance Fref Tolerance -50 50 ppm 71
Reference clock input duty cycle (crystal) Fref Duty Cycle 40 60 % 71
Crystal ESR ESR 50 ohm 71
Crystal drive level DL 0.5 mW 71
Crystal output high level Vih 1.4 V 71
Crystal output low level Vil 0.7 V 71
External clock frequency tolerance -50 50 PPM Oscillator/External clock 72
External clock duty cycle 40 60 % Oscillator/External clock 72
External clock Vih Vih 1.4 V Max is AVDD33+0.3 V 72
External clock Vil Vil 0.7 V 72
External clock rise time 10 ns 10%~90% 72
External clock fall time 10 ns 10%~90% 72
External clock frequency 25 MHz Oscillator/External clock 71

CAD (KiCad official)

  • Symbol: YT8531SC
  • Footprint: Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm
  • 3D model: QFN-48(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: yt8531sc-etched.step / yt8531sc-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); yt8531sc.step / yt8531sc.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Motorcomm datasheet (75 pp, sha256 546bbbcc952d079c, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF