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XTR106UA

Public Made by Adom

by adom

Texas Instruments Special Purpose Amplifiers, SOIC-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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docs xtr106ua: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
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page.json xtr106ua: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 20h ago
README.md xtr106ua: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 16d ago
xtr106ua-etched.fit.json xtr106ua: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
xtr106ua-etched.glb xtr106ua: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
xtr106ua-etched.step xtr106ua: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
xtr106ua.glb Publish 0.1.0 · Ray 28d ago
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xtr106ua.step Publish 0.1.0 · Ray 28d ago

XTR106UA

Texas Instruments · Special Purpose Amplifiers · SOIC-14

XTR106UA from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VREG power_out 5.1V regulator output. Provides regulated supply for external circuitry powered from the loop.
2 VIN- input Negative (inverting) differential voltage input to the instrumentation amplifier front end.
3 RG passive Input-stage gain-setting pin. External resistor RG between pins 3 and 4 sets the voltage-to-current transfer gain (S = 40 / RG A/V).
4 RG passive Input-stage gain-setting pin. External resistor RG between pins 3 and 4 sets the voltage-to-current transfer gain.
5 VIN+ input Positive (non-inverting) differential voltage input to the instrumentation amplifier front end.
6 IRET input Local ground return pin for VREG, VREF5, and VREF2.5. Sinks the reference/regulator quiescent currents back through the loop.
7 IO output Regulated 4mA to 20mA current-loop output. Drives the external NPN pass transistor via B/E to modulate loop current.
8 E input Emitter connection for the external NPN pass transistor (e.g., TIP29C) used in the loop current output stage.
9 B output Base drive for the external NPN pass transistor in the loop current output stage.
10 V+ power_in Loop supply input. Operating range 7.5V to 36V (absolute maximum 40V), referenced to the IO pin.
11 RLIN passive Linearization resistor pin. External resistor between pins 1 (VREG) and 11 sets the correction coefficient of the bridge linearization circuit.
12 Lin Polarity input Linearization polarity select. Tie to IRET for positive-going nonlinearity correction, or to VREG for negative-going correction / linearization disabled.
13 VREF2.5 power_out 2.5V precision reference / bridge excitation output.
14 VREF5 power_out 5V precision reference / bridge excitation output.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Amplifiers/Comparators
Pins 14

Ordering variants

Same part, different packaging or reel option.

  • XTR106UAU
  • XTR106UA
  • XTR106UAP
  • XTR106UAPA

CAD (KiCad official)

  • Symbol: XTR106UA
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: xtr106ua-etched.step / xtr106ua-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xtr106ua.step / xtr106ua.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (37 pp, sha256 52ca45d5b4d5d2e1, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF