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XT25F32FSSIGU

Public Made by Adom

by adom

XTX NOR FLASH, SOP-8-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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XT25F32FSSIGU

XTX · NOR FLASH · SOP-8-208mil

XT25F32FSSIGU from XTX, in a SOP-8-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS# input Chip Select Input; the datasheet gives no further electrical limits for this pin.
2 SO (IO1) bidirectional Data Output (Data Input Output 1) in standard SPI, and IO1 in Dual/Quad SPI modes.
3 WP# (IO2) bidirectional Write Protect Input (Data Input Output 2), and IO2 in Quad SPI mode; the datasheet gives no further electrical limits for this pin.
4 VSS power_in Ground.
5 SI (IO0) bidirectional Data Input (Data Input Output 0), and IO0 in Dual/Quad SPI modes.
6 SCLK input Serial Clock Input.
7 HOLD# (IO3) bidirectional Hold Input (Data Input Output 3), and IO3 in Quad SPI mode; the datasheet gives no further electrical limits for this pin.
8 VCC power_in Power Supply; the single supply voltage range is 2.7~3.6V per the datasheet.

Key specifications

Parameter Value
Manufacturer XTX
Package SOP-8-208mil
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 2.7 3.6 V 45
Ambient operating temperature TA -40 85 °C 45
Ambient operating temperature -40 85 °C 44
Storage temperature -65 150 °C 44
Output short circuit current 200 mA 44
Applied input/output voltage -0.5 4 V 44
VCC supply voltage (absolute maximum) VCC -0.5 4 V 44
Latch-up input voltage on I/O pins respect to VSS -1 V 43
Latch-up VCC current -100 100 mA 43
Write inhibit voltage VWI 1.5 2.5 V 43
Input leakage current ILI -2 2 μA 45
Output leakage current ILO -2 2 μA 45
Standby current ICC1 15 55 μA CS#=VCC, VIN=VCC or VSS 45
Deep power-down current ICC2 0.3 8 μA CS#=VCC, VIN=VCC or VSS 45
Operating current (read) at 133MHz ICC3 12 20 mA CLK=0.1VCC/0.9VCC at 133MHz, Q=Open(*1,*2,*4 I/O) 45
Operating current (read) at 80MHz ICC3 9 13 mA CLK=0.1VCC/0.9VCC at 80MHz, Q=Open(*1,*2,*4 I/O) 45
Operating current (PP) ICC4 40 mA CS#=VCC 45
Operating current (WRSR) ICC5 25 mA CS#=VCC 45
Operating current (SE) ICC6 25 mA CS#=VCC 45
Operating current (BE) ICC7 25 mA CS#=VCC 45
Operating current (CE) ICC8 25 mA CS#=VCC 45
Input low voltage VIL -0.5 V 45
Output low voltage VOL 0.2 V IOL=100uA 45
Serial clock frequency (all commands except Read, 3.0-3.6V) fC 133 MHz all commands except Read (03H), on 3.0-3.6V power supply, DC=1. 46
Serial clock frequency (all commands except Read, 2.7-3.0V) fC1 104 MHz all commands except Read (03H), on 2.7-3.0V power supply, DC=1. 46
Serial clock frequency (all commands except Read, DC=0) fC2 104 MHz all commands except Read (03H), DC=0 46
Serial clock frequency (Read) fR 80 MHz For: Read (03H) 46
Serial clock rise time (slew rate) tCLCH 0.2 V/ns 46
Serial clock fall time (slew rate) tCHCL 0.2 V/ns 46
CS# active setup time tSLCH 5 ns 46
CS# active hold time tCHSH 5 ns 46
CS# not active setup time tSHCH 5 ns 46
CS# not active hold time tCHSL 5 ns 46
CS# high time (read/write) tSHSL 20 ns 46
Output disable time tSHQZ 6 ns 46
Output hold time tCLQX 1 ns 46
Clock low to output valid tCLQV 5.5 ns 46
Data in setup time tDVCH 2 ns 46
Data in hold time tCHDX 2 ns 46
Hold# low setup time (relative to clock) tHLCH 5 ns 46
Hold# high setup time (relative to clock) tHHCH 5 ns 46
Hold# high hold time (relative to clock) tCHHL 5 ns 46
Hold# low hold time (relative to clock) tCHHH 5 ns 46
Hold# low to high-Z output tHLQZ 6 ns 46
Hold# high to low-Z output tHHQX 6 ns 46
Write protect setup time before CS# low tWHSL 20 ns 46
Write protect hold time after CS# high tSHWL 100 ns 46
CS# high to deep power-down mode tDP 3 µs 46
CS# high to standby mode without electronic signature read tRES1 20 µs 46
CS# high to standby mode with electronic signature read tRES2 20 µs 46
CS# high to next command after reset (from read) tRST_R 30 µs 46
CS# high to next command after reset (from program) tRST_P 30 µs 47
CS# high to next command after reset (from erase) tRST_E 12 ms 47
Write status register cycle time tW 3 20 ms 47
Page programming time tPP 0.4 2 ms 47
Sector erase time tSE 50 2000 ms 47
Block erase time (32K bytes) tBE1 0.15 2.2 s 47
Block erase time (64K bytes) tBE2 0.25 2.5 s 47
Chip erase time tCE 12 30 s 47

CAD (KiCad official)

  • Symbol: XT25F32FSSIGU
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8-208mil (KiCad packages3D, STEP)
  • 3D model files: xt25f32fssigu-etched.step / xt25f32fssigu-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xt25f32fssigu.step / xt25f32fssigu.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XTX datasheet (53 pp, sha256 cb75d976d76393ca, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF