XR77103ELBTR from MaxLinear, in a QFN-32-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VOUT3	input	Buck 3 output sense pin.
2	COMP3	passive	Compensation pin for Buck 3; connect a series RC circuit to this pin for compensation.
3	A0	input	I2C address select pin; A0 is internally pulled high through a 100kΩ pull-up resistor.
4	VIN	power_in	IC supply pin; connect a capacitor as close as possible to this pin and AGND. VIN, VIN1, VIN2 and VIN3 must be tied together.
5	GND	power_in	Ground.
6	VCC	power_out	Internal supply; connect a ceramic capacitor from this pin to AGND, and tie VCC to VIN for VIN = 5V.
7	COMP1	passive	Compensation pin for Buck 1; connect a series RC circuit to this pin for compensation.
8	VOUT1	input	Buck 1 output sense pin.
9	BST1	passive	Bootstrap capacitor for Buck 1; connect a bootstrap capacitor from this pin to LX1.
10	VIN1	power_in	Input supply for Buck 1; connect a capacitor as close as possible to this pin and PGND. VIN1 must be tied to VIN.
11	LX1	output	Switching node for Buck 1.
12	LX1	output	Switching node for Buck 1.
13	LX2	output	Switching node for Buck 2.
14	LX2	output	Switching node for Buck 2.
15	VIN2	power_in	Input supply for Buck 2; connect a capacitor as close as possible to this pin and PGND. VIN2 must be tied to VIN.
16	BST2	passive	Bootstrap capacitor for Buck 2; connect a bootstrap capacitor from this pin to LX2.
17	VOUT2	input	Buck 2 output sense pin.
18	COMP2	passive	Compensation pin for Buck 2; connect a series RC circuit to this pin for compensation.
19	DGND	power_in	Digital ground.
20	nWR	input	Write protection input for NVM; data can be written to NVM when this pin is low, and it is internally pulled high through a 100kΩ pull-up resistance.
21	SDA	bidirectional	Data I/O pin for the I2C serial interface.
22	SCL	input	Clock input pin for the I2C serial interface.
23	VL	power_in	Supply pin for the I2C interface; supply 3.3V typically, and it can be left floating if the I2C interface is not used.
24	PGOOD	output	Power good output; open-drain output asserted after all converters are sequenced and within regulation.
25	SYNC	input	External clock input pin; connect to AGND when unused.
26	EN	input	Enable control input; set EN high to enable converters.
27	AGND	power_in	Analog ground.
28	VIN	power_in	IC supply pin; connect a capacitor as close as possible to this pin and AGND. VIN, VIN1, VIN2 and VIN3 must be tied together.
29	LX3	output	Switching node for Buck 3.
30	LX3	output	Switching node for Buck 3.
31	VIN3	power_in	Input supply for Buck 3; connect a capacitor as close as possible to this pin and PGND. VIN3 must be tied to VIN.
32	BST3	passive	Bootstrap capacitor for Buck 3; connect a bootstrap capacitor from this pin to LX3.
33	PGND	power_in	Exposed pad is power ground (PGND); the pad number is shown as 33 in the typical application schematic.

Key specifications

Parameter	Value
Manufacturer	MaxLinear
Package	QFN-32-EP(4x4)
Category	Power Management ICs
Pins	33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VIN input voltage range	VIN	5.5		14	V	Full operating temperature range	3
VIN input voltage range, VCC tied to VIN	VIN	4.5		5.5	V	VCC tied to VIN for VIN = 5V; full operating temperature range	3
VCC internal biasing supply voltage	VCC	4.9	5	5.1	V	ILOAD = 0mA; full operating temperature range	3
Output voltage range	VOUTx	0.8		6	V	Full operating temperature range	4
Switching frequency	fSW	0.44		2.3	MHz	I2C control; full operating temperature range	4
Adjustable soft-start period range		0.5		4	ms	Full operating temperature range	4
Peak inductor current limit range	ILIMx	2		4.5	A	Full operating temperature range	4
Peak inductor current limit accuracy	ILIMx	-30		30	%	Peak inductor current limit set at 4A	4
Output voltage accuracy		-1		1	%	VIN = 12V; Normal	4
Output voltage accuracy		-2		2	%	5.5V ≤ VIN ≤ 14V; Normal; full operating temperature range	4
Synchronization range	SYNCRANGE			2.31	MHz	fSW + 5%; full operating temperature range	4
Synchronization signal minimum duty cycle	SYNCD_MIN	40			%	Full operating temperature range	4
Synchronization signal maximum duty cycle	SYNCD_MAX			60	%	Full operating temperature range	4
VCC internal biasing supply current	IVCC			10	mA	VIN = 12V; full operating temperature range	3
Input threshold high (SDA, SCL, nWR, A0)	VIH	2.45			V	VINPUT rising, VL = 3.3V; full operating temperature range	5
Input threshold low (SDA, SCL, nWR, A0)	VIL			0.95	V	VINPUT falling, VL = 3.3V; full operating temperature range	5
PGOOD output low				0.4	V	ISINK = 1mA; full operating temperature range	5
Input threshold high (SYNC, EN)	VIH	2.53			V	VINPUT rising; full operating temperature range	5
Input threshold low (SYNC, EN)	VIL			1.36	V	VINPUT falling; full operating temperature range	5
SDA logic output low voltage	VOL_I2C			0.4	V	At 3mA sink current; full operating temperature range	6
SCL clock frequency	fSCL			400	kHz	Full operating temperature range	6
SCL clock high period	tHIGH	0.6			μs	Full operating temperature range	6
SCL clock low period	tLOW	1.3			μs	Full operating temperature range	6
I2C spike rejection filter pulse width	tSP	0		50	ns	Full operating temperature range	6
I2C data setup time	tSU;DAT	100			ns	Full operating temperature range	6
I2C data hold time	tHD;DAT	0		900	ns	Full operating temperature range	6
I2C bus free time between stop and start	tBUF	1.3			μs	Full operating temperature range	6
I2C repeated start condition setup time	tSU;STA	0.6			μs	Full operating temperature range	6
I2C repeated start condition hold time	tHD;STA	0.6			μs	Full operating temperature range	6
I2C stop condition setup time	tSU;STO	0.6			μs	Full operating temperature range	6
I2C data valid time	tVD;DAT			0.9	μs	Full operating temperature range	6
I2C data valid acknowledge time	tVD;ACK			0.9	μs	Full operating temperature range	6
I2C bus capacitive load	CB			400	pF	Full operating temperature range	6
Absolute max: VIN1, VIN2, VIN3, LX1, LX2, LX3		-0.3		18	V		3
Absolute max: VL, EN, SCL, SDA, nWR, A0, VCC		-0.3		7	V		3
Absolute max: PGOOD, SYNC		-0.3		7	V		3
Absolute max: BST# to LX#		-0.3		7	V		3
Absolute max: AGND, DGND to GND		-0.3		0.3	V		3
Storage temperature		-65		150	°C		3
Junction temperature				150	°C		3
Lead temperature (soldering)				260	°C	Soldering, 10 seconds	3
ESD rating HBM				2	kV	HBM, human body model	3
Input supply voltage VIN	VIN	4.5		14	V		3
VCC supply voltage	VCC	4.5		5.5	V		3
LX# pin DC range	LX#	-0.3		14	V	Transient -1V for less than 10ns (note 1)	3
Junction temperature range	TJ	-40		125	°C		3
Thermal resistance junction-to-ambient	θJA		30		°C/W		3
A0 and nWR pull-up resistor			100		kΩ		5

CAD (KiCad official)

Symbol: XR77103ELBTR
Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
3D model: QFN-32-EP(4x4) (KiCad packages3D, STEP)
3D model files: xr77103elbtr-etched.step / xr77103elbtr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xr77103elbtr.step / xr77103elbtr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: MaxLinear datasheet (28 pp, sha256 c4640b96d4dc8c55, retrieved 2026-10-30, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

XR77103ELBTR

Verified XR77103ELBTR

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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