# XR4953C

**XNRUSEMI** · MOSFETs · SOP-8

XR4953C from XNRUSEMI, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of P-channel MOSFET 1; drain-source voltage -20V, continuous drain current -3.0A at TA=25℃. |
| 2 | G1 | input | Gate of P-channel MOSFET 1; gate-source voltage maximum ±12V, threshold -0.4V to -1.0V. |
| 3 | S2 | passive | Source of P-channel MOSFET 2; drain-source voltage -20V, continuous drain current -3.0A at TA=25℃. |
| 4 | G2 | input | Gate of P-channel MOSFET 2; gate-source voltage maximum ±12V, threshold -0.4V to -1.0V. |
| 5 | D2 | passive | Drain of P-channel MOSFET 2 (tied internally with pin 6); pulsed drain current -10A maximum. |
| 6 | D2 | passive | Drain of P-channel MOSFET 2 (tied internally with pin 5); pulsed drain current -10A maximum. |
| 7 | D1 | passive | Drain of P-channel MOSFET 1 (tied internally with pin 8); pulsed drain current -10A maximum. |
| 8 | D1 | passive | Drain of P-channel MOSFET 1 (tied internally with pin 7); pulsed drain current -10A maximum. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | XNRUSEMI |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDSS |  |  | -20 | V |  | 1 |
| Gate-Source Voltage | VGSS | -12 |  | 12 | V |  | 1 |
| Continuous Drain Current | ID |  |  | -3 | A | TA = 25℃ | 1 |
| Continuous Drain Current | ID |  |  | -2 | A | TA = 100℃ | 1 |
| Pulsed Drain Current | IDM |  |  | -10 | A | note1 (repetitive rating, pulse width limited by max junction temperature) | 1 |
| Power Dissipation | PD |  |  | 1 | W | TA = 25℃ | 1 |
| Operating and Storage Temperature Range | TJ, TSTG | -55 |  | 150 | ℃ |  | 1 |
| Thermal Resistance, Junction to Ambient | RθJA |  |  | 125 | ℃/W |  | 1 |
| Drain-Source Breakdown Voltage | V(BR)DSS | -20 |  |  | V | VGS=0V, ID= -250μA | 2 |
| Zero Gate Voltage Drain Current | IDSS |  |  | -1 | μA | VDS = -20V, VGS = 0V | 2 |
| Gate to Body Leakage Current | IGSS | -100 |  | 100 | nA | VDS =0V, VGS = ±12V | 2 |
| Gate Threshold Voltage | VGS(th) | -0.4 | -0.7 | -1 | V | VDS= VGS, ID= -250μA | 2 |
| Static Drain-Source on-Resistance | RDS(on) |  | 80 | 104 | mΩ | VGS =-4.5V, ID =-2.5A | 2 |
| Static Drain-Source on-Resistance | RDS(on) |  | 110 | 154 | mΩ | VGS =-2.5V, ID =-1.5A | 2 |
| Maximum Continuous Drain to Source Diode Forward Current | IS |  |  | -3 | A |  | 2 |
| Maximum Pulsed Drain to Source Diode Forward Current | ISM |  |  | -10 | A |  | 2 |
| Drain to Source Diode Forward Voltage | VSD |  |  | -1.2 | V | VGS = 0V, IS = -2.5A | 2 |

## CAD (KiCad official)

- Symbol: `XR4953C`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `xr4953c-etched.step` / `xr4953c-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `xr4953c.step` / `xr4953c.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [XNRUSEMI datasheet](docs/xr4953c-datasheet.pdf) (5 pp, sha256 `c21aec35cca9bb2d`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/xr4953c-datasheet.pdf)