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XR31233EDTR

Public Made by Adom

by adom

MaxLinear Pre-ordered Chips, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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XR31233EDTR

MaxLinear · Pre-ordered Chips · SOIC-8

XR31233EDTR from MaxLinear, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D input CAN transmit data input (TXD, driver input): LOW for dominant and HIGH for recessive bus states.
2 GND power_in Ground.
3 VCC power_in 3.3V power supply input (3.0V to 3.6V operating range), bypass to ground with 0.1μF capacitor.
4 R output CAN receive data output (RXD, receiver output): LOW for dominant and HIGH for recessive bus states.
5 LBK input XR31233 loopback mode input: LBK = 1 loops the D input back to the R output without driving the CAN bus, LBK = 0 is normal mode.
6 CANL bidirectional Low level CAN bus line, tolerant to -36V to 36V at the bus terminal.
7 CANH bidirectional High level CAN bus line, tolerant to -36V to 36V at the bus terminal.
8 RS input Mode select pin: strong pulldown to GND = high speed mode, strong pullup to VCC = low power mode, 10kΩ to 100kΩ pulldown to GND = slope control mode.

Key specifications

Parameter Value
Manufacturer MaxLinear
Package SOIC-8
Category Interface ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC supply range VCC 3 3.6 V 2
Operating temperature range -40 125 °C 2
Supply voltage VCC -0.3 7 V 2
Voltage at any bus terminal CANH, CANL -36 36 V 2
Transient pulse voltage, CANH and CANL -100 100 V through 100Ω (Figure 9) 2
Input voltage -0.5 7 V D, RS, EN, LBK, AB 2
Output voltage -0.5 7 V 2
Receiver output current -10 10 mA 2
Operating junction temperature 150 °C 2
Storage temperature -65 150 °C 2
Lead temperature 300 °C soldering 10 seconds 2
Bus output voltage (Dominant) CANH VO(D) 2.3 V D at 0V, RS at 0V, see Figure 3 and Figure 4 3
Bus output voltage (Dominant) CANL VO(D) 0.5 1.25 V D at 0V, RS at 0V, see Figure 3 and Figure 4 3
Differential output voltage (Dominant) VOD(D) 1.5 2 3 V D at 0V, RS at 0V, see Figure 3 and Figure 4 3
Differential output voltage (Dominant) VOD(D) 1.2 2 3 V D at 0V, RS at 0V, see Figure 4 and Figure 5 3
Differential output voltage (Recessive) VOD -120 12 mV D at 3V, RS at 0V, see Figure 3 and Figure 4 3
Differential output voltage (Recessive) VOD -0.5 0.05 V D at 3V, RS at 0V, No Load 3
Peak-to-peak common-mode output voltage VOC(PP) 1 V See Figure 12 3
High-level input current D, EN, LBK, AB IIH -30 30 μA D = 2V or EN = 2V or LBK = 2V or AB = 2V 3
Low-level input current D, EN, LBK, AB IIL -30 30 μA D = 0.8V or EN = 0.8V or LBK = 0.8V or AB = 0.8V 3
Short-circuit output current IOS -250 mA VCANH = -25V, CANL Open, see Figure 17 3
Short-circuit output current IOS 3 mA VCANH = 25V, CANL Open, see Figure 17 3
Short-circuit output current IOS -3 mA VCANH = -25V, CANH Open, see Figure 17 3
Short-circuit output current IOS 250 mA VCANH = 25V, CANH Open, see Figure 17 3
RS input current for standby IIRS(S) -10 μA RS at 0.75 Vcc 3
Supply current, Standby ICC 200 600 μA RS at VCC, D at VCC, AB at 0V, LBK at 0V, EN at VCC 3
Supply current, Dominant ICC 6 mA D at 0V, No Load, AB at 0V, LBK at 0V 3
Supply current, Recessive ICC 6 mA D at VCC, No Load, AB at 0V, LBK at 0V, RS at 0V, EN at VCC 3
Positive-going input threshold voltage VIT+ 750 900 mV AB at 0V, LBK at 0V, EN at VCC, see Table 1 4
Negative-going input threshold voltage VIT- 500 650 mV AB at 0V, LBK at 0V, EN at VCC, see Table 1 4
Hysteresis voltage VHYS 100 mV VIT+ to VIT- 4
High-level output voltage VOH 2 V VCC < 3.3V, IO = -4mA, see Figure 8 4
High-level output voltage VOH 2.4 V VCC ≥ 3.0V, IO = -4mA, see Figure 8 4
Low-level output voltage VOL 0.4 V IO = 4mA, see Figure 8 4
Bus input current II 400 1250 μA CANH or CANL at 25V, other bus pin at 0V, D at 3V, AB at 0V, LBK at 0V, RS at 0V, EN at VCC 4
Bus input current II -1400 -500 μA CANH or CANL at -25V, other bus pin at 0V, D at 3V, AB at 0V, LBK at 0V, RS at 0V, EN at VCC 4
Input capacitance (CANH or CANL) CI 40 pF Pin-to-ground, VI = 0.4 sin (4E6πt) + 0.5V, D at 3V, AB at 0V, LBK at 0V, EN at VCC 4
Differential input capacitance CID 20 pF Pin-to-pin, VI = 0.4 sin (4E6πt) + 0.5V, D at 3V, AB at 0V, LBK at 0V, EN at VCC 4
Differential input resistance RID 40 100 kΩ D at 3V, AB at 0V, LBK at 0V, EN at VCC 4
Input resistance (CANH or CANL) to ground RIN 20 50 kΩ D at 3V, AB at 0V, LBK at 0V, EN at VCC 4
Driver propagation delay low-to-high tPLH 35 85 ns RS at 0V, see Figure 6 5
Driver propagation delay low-to-high tPLH 70 125 ns RS with 10kΩ to ground, see Figure 6 5
Driver propagation delay low-to-high tPLH 500 870 ns RS with 100kΩ to ground, see Figure 6 5
Driver propagation delay high-to-low tPHL 70 120 ns RS at 0V, see Figure 6 5
Driver propagation delay high-to-low tPHL 130 180 ns RS with 10kΩ to ground, see Figure 6 5
Driver propagation delay high-to-low tPHL 870 1200 ns RS with 100kΩ to ground, see Figure 6 5
Driver pulse skew tsk(p) 35 ns RS at 0V, see Figure 6 5
Driver pulse skew tsk(p) 60 ns RS with 10kΩ to ground, see Figure 6 5
Driver pulse skew tsk(p) 370 ns RS with 100kΩ to ground, see Figure 6 5
Differential output rise time tr 5 70 ns RS at 0V, see Figure 6 5
Differential output fall time tf 5 70 ns RS at 0V, see Figure 6 5
Differential output rise time tr 30 135 ns RS with 10kΩ to ground, see Figure 6 5
Differential output fall time tf 30 135 ns RS with 10kΩ to ground, see Figure 6 5
Differential output rise time tr 350 1400 ns RS with 100kΩ to ground, see Figure 6 5
Differential output fall time tf 350 1400 ns RS with 100kΩ to ground, see Figure 6 5
Enable time from standby to dominant ten(s) 0.6 1.5 μs See Figure 10 5
Receiver propagation delay low-to-high tPLH 35 60 ns See Figure 8 5
Receiver propagation delay high-to-low tPHL 35 60 ns See Figure 8 5
Receiver pulse skew tsk(p) 7 ns See Figure 8 5
Loopback delay, driver input to receiver output t(LBK) 7.5 12 ns XR31233, See Figure 14 6
Total loop delay, recessive to dominant t(loop1) 70 135 ns RS at 0V, see Figure 13 6
Total loop delay, dominant to recessive t(loop2) 70 135 ns RS at 0V, See Figure 13 6

CAD (KiCad official)

  • Symbol: XR31233EDTR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: xr31233edtr-etched.step / xr31233edtr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xr31233edtr.step / xr31233edtr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: MaxLinear datasheet (16 pp, sha256 64dd288d5223a33a, retrieved 2026-10-26, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF