component

XR3082XIDTR-F

Public Made by Adom

by adom

MaxLinear Pre-ordered Chips, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterface icsxr3082xidtr-ffactory-2.0.0extractor-text

Verified XR3082XIDTR-F

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: XR3082XIDTR-F · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 24-page datasheet
  • ✓distributor: lcsc C2672009, digikey 1016-XR3082XIDTR-FTR-ND, mouser 701-XR3082XID/TR-F
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-db26wviu/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ xr3082xidtr-f.kicad_sym✓ xr3082xidtr-f.kicad_mod✓ xr3082xidtr-f.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 10d ago
viewers xr3082xidtr-f: viewers · Ray 10d ago
package.json Publish 0.1.0 · Ray 10d ago
page.json Set visibility: public · Ray 10d ago
README.md Publish 0.1.0 · Ray 10d ago
verification.json Verified: Published by the parts factory: tier mfr, 8 pins · Ray 10d ago
xr3082xidtr-f-etched.glb Publish 0.1.0 · Ray 10d ago
xr3082xidtr-f-etched.step xr3082xidtr-f: factory component page (tier=mfr) · Ray 10d ago
xr3082xidtr-f-hero.glb xr3082xidtr-f: hero GLB from the etched model (keeps the MPN mark) · Ray 10d ago
xr3082xidtr-f-hero.overlay.json Publish 0.1.0 · Ray 10d ago
xr3082xidtr-f.glb Publish 0.1.0 · Ray 10d ago
xr3082xidtr-f.kicad_mod Publish 0.1.0 · Ray 10d ago
xr3082xidtr-f.kicad_sym Publish 0.1.0 · Ray 10d ago
xr3082xidtr-f.lbr Publish 0.1.0 · Ray 10d ago
xr3082xidtr-f.step Publish 0.1.0 · Ray 10d ago

XR3082XIDTR-F

MaxLinear · Pre-ordered Chips · SOIC-8

XR3082XIDTR-F from MaxLinear, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RO output Receiver output: when RE is low, RO is high if (A-B) ≥ -50mV and low if (A-B) ≤ -200mV.
2 RE input Receiver output enable (hot swap): low enables RO, high puts RO in high impedance, and RE high with DE low enters shutdown mode.
3 DE input Driver output enable (hot swap): high enables the driver outputs, low puts them in high impedance, and DE low with RE high enters shutdown mode.
4 DI input Driver input: with DE high, a low on DI forces the non-inverting output low and inverting output high, and a high on DI does the opposite.
5 GND power_in Ground.
6 A bidirectional Non-inverting receiver input and non-inverting driver output, tolerant to ±18V on the bus pin.
7 B bidirectional Inverting receiver input and inverting driver output, tolerant to ±18V on the bus pin.
8 VCC power_in +5.0V power supply input (4.5V to 5.5V), bypass to ground with a 0.1µF capacitor.

Key specifications

Parameter Value
Manufacturer MaxLinear
Package SOIC-8
Category Interface ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage Range VCC 4.5 5.5 V 4
Differential Driver Output, no load VOD 3 V No Load 4
Differential Driver Output RS-422 VOD 3 V RL = 100 (RS-422), Figure 3 4
Differential Driver Output RS-485 VOD 2.1 V RL = 54 (RS-485), Figure 3 4
Differential Driver Output over common mode VOD 2.1 V -7V ≤ VCM ≤ +12V, Figure 4 4
Change in Magnitude of Differential Output Voltage ΔVOD -0.2 0.2 V RL = 100 (RS-422), or RL = 54 (RS-485), Figure 3, Note 1 4
Change in Magnitude of Common-Mode Output Voltage ΔVCM -0.2 0.2 V 4
Logic Input High Threshold VIH 2 V Logic Input High (DI, DE, RE) 4
Logic Input Low Threshold VIL 0.8 V Logic Input Low (DI, DE, RE) 4
Input Hysteresis (DI, DE, RE) VHYS 100 mV 4
Logic Input Current (DI, DE, RE) IIN -1 1 µA 0V ≤ VIN ≤ VCC, After first transition, Note 2 4
Logic Input Current (DE and RE) IIN -200 100 200 µA Until first transition, Note 2 4
Input Current (A and B) high IA, B 125 µA VOUT = +12V, DE = 0V, VCC = 0V or 5.5V 4
Input Current (A and B) low IA, B -100 µA VOUT = -7V, DE = 0V, VCC = 0V or 5.5V 4
Driver Short-Circuit Output Current IOSD -250 250 mA -7V ≤ VOUT ≤ +12V, Figure 5 4
Thermal Shutdown Temperature TTS 175 °C Junction temperature, Note 4 4
Thermal Shutdown Hysteresis TTSH 15 °C Note 4 4
Receiver Differential Threshold Voltage (VA - VB) VTH -200 -125 -50 mV -7V ≤ VCM ≤ +12V 5
Receiver Input Hysteresis 25 mV VCM = 0V 5
Receiver Output Low Voltage (RO) VOL 0.4 V IOUT = 4mA 5
High-Z Receiver Output Current IOZR -1 1 µA 0V ≤ VOUT ≤ VCC 5
Receiver Input Resistance RIN 96 kΩ -7V ≤ VCM ≤ +12V 5
Receiver Output Short-Circuit Current IOSC -95 95 mA 0V ≤ VRO ≤ VCC 5
Supply Current, driver on ICC 425 600 µA No Load, RE = 0V, DE = VCC, DI = 0V 5
Supply Current, driver on receiver off ICC 330 600 µA No Load, RE = VCC, DE = VCC, DI = 0V 5
Supply Current, idle ICC 300 600 µA No Load, RE = 0V, DE = 0V, Receiver A and B inputs open 5
Supply Current in Shutdown Mode ISHDN 0.001 1 µA RE = VCC, DE = 0V, Temperature grade I 5
Driver Prop. Delay (Low to High) tDPLH 350 1500 ns CL = 50pF, RL = 54, Figure 7 6
Driver Prop. Delay (High to Low) tDPHL 350 1500 ns CL = 50pF, RL = 54, Figure 7 6
Differential Driver Output Skew /tDPLH-tDPHL/ 20 200 ns CL = 50pF, RL = 54, Figure 7 6
Driver Differential Output Rise or Fall Time tDR, tDF 400 1500 ns CL = 50pF, RL = 54, Figure 7 6
Driver Maximum Data Rate 250 kbps 1/tUI, Duty Cycle 40 to 60% 6
Driver Enable to Output High tDZH 200 2500 ns CL = 50pF, RL = 500, Figure 8 6
Driver Enable to Output Low tDZL 200 2500 ns CL = 50pF, RL = 500, Figure 8 6
Driver Disable from Output High tDHZ 6 100 ns CL = 50pF, RL = 500, Figure 8 6
Driver Disable from Output Low tDLZ 6 100 ns CL = 50pF, RL = 500, Figure 8 6
Driver Enable from Shutdown to Output High tDZH(SHDN) 5500 ns CL = 50pF, RL = 500, Figure 8 6
Driver Enable from Shutdown to Output Low tDZL(SHDN) 5500 ns CL = 50pF, RL = 500, Figure 8 6
Time to Shutdown tSHDN 50 200 600 ns Notes 3 and 4 6
Receiver Prop. Delay (Low to High) tRPLH 200 ns CL = 15pF, VID = ±2V, VID Rise and Fall times < 15ns, Figure 9 6
Receiver Prop. Delay (High to Low) tRPHL 200 ns CL = 15pF, VID = ±2V, VID Rise and Fall times < 15ns, Figure 9 6
Receiver Propagation Delay Skew /tRPLH-tRPHL/ 30 ns CL = 15pF, VID = ±2V, Figure 9 6
Receiver Maximum Data Rate 250 kbps 1/tUI, Duty Cycle 40 to 60% 6
Receiver Enable to Output High tRZH 50 ns CL = 15pF, RL = 1k, Figure 10 6
Receiver Enable to Output Low tRZL 50 ns CL = 15pF, RL = 1k, Figure 10 6
Receiver Disable from Output High tRHZ 50 ns CL = 15pF, RL = 1k, Figure 10 6
Receiver Disable from Output Low tRLZ 50 ns CL = 15pF, RL = 1k, Figure 10 6
Receiver Enable from Shutdown to Output High tRZH(SHDN) 3500 ns CL = 15pF, RL = 1k, Figure 10 6
Receiver Enable from Shutdown to Output Low tRZL(SHDN) 3500 ns CL = 15pF, RL = 1k, Figure 10 6
Supply Voltage VCC -0.3 7 V 2
Input Voltage at Control and Driver Input (RE, DE, DI) -0.3 7 V 2
Driver Output Voltage (A, B, Y and Z) -18 18 V 2
Receiver Input Voltage (A and B) -18 18 V half or full duplex 2
Transient Voltage Pulse -70 70 V through 100, Figure 6 2
Driver Output Current -250 250 mA 2
Storage Temperature Range -65 150 °C 2
Lead Temperature (soldering, 10s) 300 °C 2
Maximum Junction Temperature 150 °C 2
Operating Temperature Range (Industrial) -40 85 °C Temperature grade I 3
Thermal Resistance, 8-Pin SO θJA 128.4 °C/W Package Power Dissipation, 8-Pin SO 2

CAD (KiCad official)

  • Symbol: XR3082XIDTR-F
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: xr3082xidtr-f-etched.step / xr3082xidtr-f-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xr3082xidtr-f.step / xr3082xidtr-f.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: MaxLinear datasheet (24 pp, sha256 891f1bb4ca559553, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF