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XMC4300F100F256AA

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Infineon Technologies Infineon, TQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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XMC4300F100F256AA

Infineon Technologies · Infineon · TQFP-100(14x14)

XMC4300F100F256AA from Infineon Technologies, in a TQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P0.1 bidirectional General-purpose port pin P0.1 with A1+ pad class (weak/medium/strong driver, VIH min 0.6×VDDP); datasheet notes it as an alternate-function pin (e.g. USB DRIVEVBUS, USIC, CCU8 outputs).
2 P0.0 bidirectional General-purpose port pin P0.0 with A1+ pad class (weak/medium/strong driver, VIH min 0.6×VDDP).
3 P0.10 bidirectional General-purpose port pin P0.10 with A1+ pad class (weak/medium/strong driver, VIH min 0.6×VDDP).
4 P0.9 bidirectional General-purpose port pin P0.9 with A2 pad class (weak/medium/strong driver, VIH min 0.6×VDDP).
5 P3.2 bidirectional General-purpose port pin P3.2 with A2 pad class (weak/medium/strong driver, VIH min 0.6×VDDP).
6 P3.1 bidirectional General-purpose port pin P3.1 with A2 pad class (weak/medium/strong driver, VIH min 0.6×VDDP).
7 P3.0 bidirectional General-purpose port pin P3.0 with A2 pad class (weak/medium/strong driver, VIH min 0.6×VDDP).
8 USB_DM bidirectional USB OTG data line D- (special pad); USB 2.0 full-speed, high-speed mode not supported.
9 USB_DP bidirectional USB OTG data line D+ (special pad); USB 2.0 full-speed, high-speed mode not supported.
10 VBUS power_in USB VBUS sense input (special pad) with input voltage range 0.0 to 5.25 V.
11 VDDP power_in Digital I/O supply voltage (power pin).
12 VDDC power_in Core supply voltage pin; 100 nF capacitor required on each VDDC pin plus 10 µF external buffer capacitor.
13 HIB_IO_1 bidirectional Hibernate domain I/O (A1 special pad, supplied by VBAT); after hibernate-domain reset it is an input with no pull device, medium driver mode as output.
14 HIB_IO_0 bidirectional Hibernate domain I/O (A1 special pad, supplied by VBAT); after hibernate-domain reset it is an open-drain output driving 0, medium driver mode as output.
15 RTC_XTAL2 output Output of the 32.768 kHz RTC crystal oscillator (clock_O).
16 RTC_XTAL1 input Input of the 32.768 kHz RTC crystal oscillator or external clock input (clock_IN).
17 VBAT power_in Hibernate domain battery supply; must be supplied whenever VDDP is supplied (3.0 V or more needed for reliable RTC crystal start).
18 P15.3 input Analog/digital input port pin P15.3 (AN/DIG_IN).
19 P15.2 input Analog/digital input port pin P15.2 (AN/DIG_IN).
20 P14.15 input Analog/digital input port pin P14.15 (AN/DIG_IN).
21 P14.14 input Analog/digital input port pin P14.14 (AN/DIG_IN).
22 P14.13 input Analog/digital input port pin P14.13 (AN/DIG_IN).
23 P14.12 input Analog/digital input port pin P14.12 (AN/DIG_IN).
24 P14.7 input Analog/digital input port pin P14.7 (AN/DIG_IN).
25 P14.6 input Analog/digital input port pin P14.6 (AN/DIG_IN).
26 P14.5 input Analog/digital input port pin P14.5 (AN/DIG_IN).
27 P14.4 input Analog/digital input port pin P14.4 (AN/DIG_IN).
28 P14.3 input Analog/digital input port pin P14.3 (AN/DIG_IN).
29 P14.2 input Analog/digital input port pin P14.2 (AN/DIG_IN).
30 P14.1 input Analog/digital input port pin P14.1 (AN/DIG_IN).
31 P14.0 input Analog/digital input port pin P14.0 (AN/DIG_IN).
32 VAGND power_in ADC reference ground (AN_Ref); must be between VSSM-0.05 V and VAREF-1 V.
33 VAREF power_in ADC reference voltage (AN_Ref); range VAGND+1 V to VDDA+0.05 V.
34 VSSA power_in Analog supply ground (AN_Power).
35 VDDA power_in Analog supply voltage for ADC and DAC (AN_Power).
36 P14.9 bidirectional Analog/DAC/digital input port pin P14.9 (AN/DAC/DIG_IN) that also carries a DAC output function.
37 P14.8 bidirectional Analog/DAC/digital input port pin P14.8 (AN/DAC/DIG_IN) that also carries a DAC output function.
38 P15.9 input Analog/digital input port pin P15.9 (AN/DIG_IN).
39 P15.8 input Analog/digital input port pin P15.8 (AN/DIG_IN).
40 P2.15 bidirectional General-purpose port pin P2.15 with A2 pad class.
41 P2.14 bidirectional General-purpose port pin P2.14 with A2 pad class.
42 VDDC power_in Core supply voltage pin; 100 nF capacitor required on each VDDC pin plus 10 µF external buffer capacitor.
43 VDDP power_in Digital I/O supply voltage (power pin).
44 P2.10 bidirectional General-purpose port pin P2.10 with A2 pad class.
45 P2.9 bidirectional General-purpose port pin P2.9 with A2 pad class.
46 P2.8 bidirectional General-purpose port pin P2.8 with A2 pad class.
47 P2.5 bidirectional General-purpose port pin P2.5 with A2 pad class.
48 P2.4 bidirectional General-purpose port pin P2.4 with A2 pad class.
49 P2.3 bidirectional General-purpose port pin P2.3 with A2 pad class.
50 P2.2 bidirectional General-purpose port pin P2.2 with A2 pad class.
51 P2.1 bidirectional Port pin P2.1 (A2 pad); after a system reset, via HWSEL, it selects the DB.TDO function.
52 P2.0 bidirectional General-purpose port pin P2.0 with A2 pad class.
53 P2.7 bidirectional General-purpose port pin P2.7 with A1+ pad class.
54 P2.6 bidirectional General-purpose port pin P2.6 with A1+ pad class.
55 P5.7 bidirectional General-purpose port pin P5.7 with A1+ pad class.
56 P5.2 bidirectional General-purpose port pin P5.2 with A1+ pad class.
57 P5.1 bidirectional General-purpose port pin P5.1 with A1+ pad class.
58 P5.0 bidirectional General-purpose port pin P5.0 with A1+ pad class.
59 VSS power_in Digital ground (power pin).
60 VDDP power_in Digital I/O supply voltage (power pin).
61 XTAL1 input Main oscillator input (clock_IN), 4 to 25 MHz crystal mode or 4 to 40 MHz direct input mode.
62 XTAL2 output Main oscillator output (clock_O) to the crystal; left unconnected-driven in direct input mode.
63 VSSO power_in I/O ground supply pin (power pin).
64 VDDC power_in Core supply voltage pin; 100 nF capacitor required on each VDDC pin plus 10 µF external buffer capacitor.
65 PORST input Power-on reset input with weak pull-up permanently active and strong pull-down controlled by EVR; spike filter blocks pulses up to 10 ns and passes pulses of 100 ns or more.
66 TMS bidirectional JTAG/SWD test mode select (A1+ pad) with weak pull-up active; strong-soft driver mode as output.
67 TCK input JTAG/SWD test clock (A1 pad) with weak pull-down active.
68 P1.15 bidirectional General-purpose port pin P1.15 with A2 pad class.
69 P1.14 bidirectional General-purpose port pin P1.14 with A2 pad class.
70 P1.13 bidirectional General-purpose port pin P1.13 with A2 pad class.
71 P1.12 bidirectional General-purpose port pin P1.12 with A2 pad class.
72 P1.11 bidirectional General-purpose port pin P1.11 with A1+ pad class.
73 P1.10 bidirectional General-purpose port pin P1.10 with A1+ pad class.
74 P1.5 bidirectional General-purpose port pin P1.5 with A1+ pad class.
75 P1.4 bidirectional General-purpose port pin P1.4 with A1+ pad class.
76 P1.3 bidirectional General-purpose port pin P1.3 with A2 pad class.
77 P1.2 bidirectional General-purpose port pin P1.2 with A2 pad class.
78 P1.1 bidirectional General-purpose port pin P1.1 with A1+ pad class.
79 P1.0 bidirectional General-purpose port pin P1.0 with A1+ pad class.
80 P1.9 bidirectional General-purpose port pin P1.9 with A2 pad class.
81 P1.8 bidirectional General-purpose port pin P1.8 with A2 pad class.
82 P1.7 bidirectional General-purpose port pin P1.7 with A2 pad class.
83 P1.6 bidirectional General-purpose port pin P1.6 with A2 pad class.
84 P4.1 bidirectional General-purpose port pin P4.1 with A2 pad class.
85 P4.0 bidirectional General-purpose port pin P4.0 with A2 pad class.
86 VDDC power_in Core supply voltage pin; 100 nF capacitor required on each VDDC pin plus 10 µF external buffer capacitor.
87 VDDP power_in Digital I/O supply voltage (power pin).
88 P0.8 bidirectional Port pin P0.8 (A2 pad); after a system reset, via HWSEL, it selects the DB.TRST function with a weak pull-down active.
89 P0.7 bidirectional Port pin P0.7 (A2 pad); after a system reset, via HWSEL, it selects the DB.TDI function.
90 P3.6 bidirectional General-purpose port pin P3.6 with A2 pad class.
91 P3.5 bidirectional General-purpose port pin P3.5 with A2 pad class.
92 P3.4 bidirectional General-purpose port pin P3.4 with A1+ pad class.
93 P3.3 bidirectional General-purpose port pin P3.3 with A1+ pad class.
94 P0.12 bidirectional General-purpose port pin P0.12 with A1+ pad class.
95 P0.11 bidirectional General-purpose port pin P0.11 with A1+ pad class.
96 P0.6 bidirectional General-purpose port pin P0.6 with A2 pad class.
97 P0.5 bidirectional General-purpose port pin P0.5 with A2 pad class.
98 P0.4 bidirectional General-purpose port pin P0.4 with A2 pad class.
99 P0.3 bidirectional General-purpose port pin P0.3 with A2 pad class.
100 P0.2 bidirectional General-purpose port pin P0.2 with A2 pad class.

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package TQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage temperature TST -65 150 °C 28
Junction temperature TJ -40 150 °C 28
Voltage at 3.3 V power supply pins with respect to VSS VDDP 4.3 V 28
Voltage on any Class A and dedicated input pin with respect to VSS VIN -1 4.3 V max VDDP + 1.0 or max. 4.3 V, whichever is lower 28
Voltage on any analog input pin with respect to VAGND VAIN, VAREF -1 4.3 V max VDDP + 1.0 or max. 4.3 V, whichever is lower 28
Input current on any pin during overload condition IIN -10 10 mA 28
Absolute maximum sum of all input circuit currents for one port group during overload ΣIIN -25 25 mA 28
Absolute maximum sum of all input circuit currents during overload ΣIIN -100 100 mA 28
Ambient temperature TA -40 85 °C Temp. Range F 33
Core supply voltage VDDC 1.3 V Generated internally 33
Analog ground voltage for VDDA VSSA -0.1 0 0.1 V 33
System frequency fSYS 144 MHz 33
Short circuit current of digital outputs ISC -5 5 mA 33
Absolute sum of short circuit currents per pin group ΣISC_PG 20 mA 33
Absolute sum of short circuit currents of the device ΣISC_D 100 mA 33
Thermal resistance junction-ambient RΘJA 22.5 K/W PG-LQFP-100-25, TJ ≤ 150 °C, 4-layer JEDEC board, exposed pad soldered 98
Input current on any port pin during overload condition IOV -5 5 mA 30
Absolute sum of overload currents for one port group IOVG 20 mA Σ/IOVx/, for all IOVx < 0 mA 30
Absolute sum of all overload currents IOVS 80 mA ΣIOVG 30
Pin capacitance (digital inputs/outputs) CIO 10 pF 34
PORST pull-down current /IPPD/ 13 mA VIN = 1.0 V 34
Input leakage current Class A1 IOZA1 -500 500 nA 0 V ≤ VIN ≤ VDDP 36
Input leakage current Class A1+ IOZA1+ -1 1 μA 0V ≤ VIN ≤ VDDP 36
Output low voltage Class A1 VOLA1 0.4 V IOL ≤ 2 mA; POD = medium 36
Input leakage at analog inputs IOZ1 -100 200 nA 0.03 × VDDA < VAIN < 0.97 × VDDA 41
Internal ADC clock fADCI 2 36 MHz VDDA = 3.3 V 41
Total unadjusted error TUE -4 4 LSB 12-bit resolution; VDDA = 3.3 V; VAREF = VDDA 42
Differential non-linearity error EADNL -3 3 LSB 12-bit resolution; VDDA = 3.3 V; VAREF = VDDA 42
Integral non-linearity EAINL -3 3 LSB 12-bit resolution; VDDA = 3.3 V; VAREF = VDDA 42
ADC VDDA supply current per active converter IDDAA 1.5 2 mA during conversion, VDDP = 3.6 V, TJ = 150 °C 42
DAC RMS supply current IDD 2.5 4 mA per active DAC channel, without load currents of DAC outputs 45
DAC integral non-linearity INL -5.5 2.5 5.5 LSB RL ≥ 5 kOhm, CL ≤ 50 pF 45
DAC differential non-linearity DNL -2 1 2 LSB RL ≥ 5 kOhm, CL ≤ 50 pF 45
DAC gain error EDG_IN -6.5 -1.5 3 % 46
ORC DC switching level VODC 100 125 210 mV VAIN ≥ VAREF + VODC 48
Temperature sensor range TSR -40 150 °C 50
Fast internal clock nominal frequency (calibrated) fOFINC 24 MHz calibrated 68
Fast internal clock accuracy, automatic calibration ΔfOFI -0.5 0.5 % automatic calibration 68
Slow internal clock accuracy ΔfOSI -4 4 % VBAT = const., 0 °C ≤ TA ≤ 85 °C 69
Active supply current, peripherals enabled IDDPA 135 mA 144 / 144 / 144 MHz, VDDP = 3.3 V, TA = 25 °C 57
Worst case active supply current IDDPA 250 mA VDDP = 3.6 V, TJ = 150 °C 58
Hibernate supply current, RTC on IDDPH 8.7 μA VBAT = 3.3 V 58
IDDP current at PORST low IDDP_PORST 13 55 mA VDDP = 3.6 V, TJ = 150 °C 58
Power dissipation PDISS 1.4 W VDDP = 3.6 V, TJ = 150 °C 58
PLL VCO frequency range fVCO 260 520 MHz 67

CAD (KiCad official)

  • Symbol: XMC4300F100F256AA
  • Footprint: Package_QFP:TQFP-100_14x14mm_P0.5mm
  • 3D model: TQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: xmc4300f100f256aa-etched.step / xmc4300f100f256aa-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xmc4300f100f256aa.step / xmc4300f100f256aa.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (102 pp, sha256 0ac844512e2d4bad, retrieved 2026-10-26, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF