# XL75176AD

**XINLUDA** · RS-485 / RS-422 ICs · SOP-8

XL75176AD from XINLUDA, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | R | output | Logic data output from the RS-485 receiver; the receiver output goes high impedance when RE is high (Table 3). |
| 2 | RE | input | Receive enable input, active low; it is a TTL input with VIH of 2 V minimum and VIL of 0.8 V maximum. |
| 3 | DE | input | Driver enable input, active high; it is a TTL input with VIH of 2 V minimum and VIL of 0.8 V maximum, and the driver outputs are high impedance when DE is low. |
| 4 | D | input | Logic data input to the RS-485 driver; it is a TTL input with VIH of 2 V minimum and VIL of 0.8 V maximum. |
| 5 | GND | power_in | Device ground pin; all voltages except differential bus voltage are referenced to network ground. |
| 6 | A | bidirectional | Non-inverting RS-422 or RS-485 differential data line (I/O bus port); bus terminal voltage is limited to −7 V to 12 V (common mode), and the differential voltage is measured A with respect to B. |
| 7 | B | bidirectional | Inverting RS-422 or RS-485 differential data line (I/O bus port); bus terminal voltage is limited to −7 V to 12 V (common mode), and the differential voltage is measured A with respect to B. |
| 8 | VCC | power_in | Power input; connect to a 5-V supply, with recommended supply range of 4.75 V to 5.25 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | SOP-8 |
| Category | Interface |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC |  |  | 7 | V |  | 4 |
| Voltage range at any bus terminal |  | -10 |  | 15 | V |  | 4 |
| Enable input voltage | VI |  |  | 5.5 | V |  | 4 |
| Operating free-air temperature range | TA | -40 |  | 85 | °C |  | 4 |
| Storage temperature range | Tstg | 65 |  | 150 | °C |  | 4 |
| Supply Voltage | VCC | 4.75 | 5 | 5.25 | V |  | 4 |
| Voltage at any bus terminal (separately or common mode) | VI or VIC | -7 |  | 12 | V |  | 4 |
| High-level input voltage | VIH | 2 |  |  | V | D, DE, and RE | 4 |
| Low-level input voltage | VIL |  |  | 0.8 | V | D, DE, and RE | 4 |
| Differential input voltage | VID | -12 |  | 12 | V |  | 4 |
| High-level output current, driver | IOH | -60 |  |  | mA | Driver | 4 |
| High-level output current, receiver | IOH | -400 |  |  | µA | Receiver | 4 |
| Low-level output current, driver | IOL |  |  | 60 | mA | Driver | 4 |
| Low-level output current, receiver | IOL |  |  | 8 |  | Receiver | 4 |
| Operating free-air temperature | TA | 0 |  | 70 | °C |  | 4 |
| Input clamp voltage | VIK |  |  | -1.5 | V | II = -18 mA | 5 |
| High-level output voltage | VOH | 3.7 |  |  | V | VIH = 2 V, VIL = 0.8 V, IOH = -33 mA | 5 |
| Low-level output voltage | VOL |  |  | 1.1 | V | VIH = 2 V, VIL = 0.8 V, IOH = 33 mA | 5 |
| Differential output voltage | /VOD2/ | 2 | 2.7 |  | V | RL = 100 Ω, see Figure 8 | 5 |
| Differential output voltage | /VOD2/ | 1.5 | 2.4 |  | V | RL = 54 Ω, see Figure 8 | 5 |
| Change in magnitude of differential output voltage | Δ/VOD/ | -0.2 |  | 0.2 | V |  | 5 |
| Common-mode output voltage | VOC |  |  | 3 | V | RL = 54 Ω or 100 Ω, see Figure 8 | 5 |
| Change in magnitude of common-mode output voltage | Δ/VOC/ | -0.2 |  | 0.2 | V |  | 5 |
| Output current, output disabled | IO |  |  | 1 | mA | Output disabled; VO = 12 V | 5 |
| Output current, output disabled | IO | -0.8 |  |  | mA | Output disabled; VO = -7 V | 5 |
| High-level input current | IIH |  |  | 20 | µA | VI = 2.4 V | 5 |
| Low-level input current | IIL |  |  | -400 | µA | VI = 0.4 V | 5 |
| Short-circuit output current | IOS | -250 |  |  | mA | VO = -7 V | 5 |
| Short-circuit output current | IOS |  |  | 250 | mA | VO = VCC | 5 |
| Short-circuit output current | IOS |  |  | 500 | mA | VO = 12 V | 5 |
| Supply current (total package), driver table | ICC |  | 35 | 50 | mA | No load; outputs enabled | 5 |
| Supply current (total package), driver table | ICC |  | 26 | 40 | mA | No load; outputs disabled | 5 |
| Positive-going input threshold voltage | VIT+ |  |  | 0.2 | V | VO = 2.7 V, IO = -0.4 mA | 5 |
| Negative-going input threshold voltage | VIT- | -0.2 |  |  | V | VO = 0.5 V, IO = 8 mA | 5 |
| Enable clamp voltage | VIK |  |  | -1.5 | V | II = -18 mA | 5 |
| High-level output voltage | VOH | 2.7 |  |  | V | VID = 200 mV, IOH = -400 µA; See Figure 9 | 5 |
| Low-level output voltage | VOL |  |  | 0.45 | V | VID = 200 mV, IOH = 8 mA; See Figure 9 | 5 |
| High-impedance-state output current | IOZ | -20 |  | 20 | µA | VO = 0.4 V to 2.4 V | 5 |
| Line input current | II |  |  | 1 | mA | Other input = 0 V; VI = 12 V | 5 |
| Line input current | II | -0.8 |  |  | mA | Other input = 0 V; VI = -7 V | 5 |
| High-level enable input current | IIH |  |  | 20 | µA | VIH = 2.7 V | 5 |
| Low-level enable input current | IIL |  |  | -100 | µA | VIL = 0.4 V | 5 |
| Input resistance | ri | 12 |  |  | kΩ |  | 5 |
| Short-circuit output current | IOS | -85 |  | -15 | mA |  | 5 |
| Supply current (total package), receiver table | ICC |  | 35 | 50 | mA | No load; outputs enabled | 5 |
| Supply current (total package), receiver table | ICC |  | 26 | 40 | mA | No load; outputs disabled | 5 |
| Differential-output delay time | td(OD) |  | 40 | 60 | ns | RL = 60 Ω, See Figure 10 | 6 |
| Differential-output transition time | tt(OD) |  | 65 | 95 | ns |  | 6 |
| Output enable time to high level | tPZH |  | 55 | 90 | ns | RL = 110 Ω, See Figure 11 | 6 |
| Output enable time to low level | tPZL |  | 30 | 50 | ns | RL = 110 Ω, See Figure 12 | 6 |
| Output disable time from high level | tPHZ |  | 85 | 130 | ns | RL = 110 Ω, See Figure 11 | 6 |
| Output disable time from low level | tPLZ |  | 20 | 40 | ns | RL = 110 Ω, See Figure 12 | 6 |
| Propagation delay time, low-to-high-level output | tPLH |  | 21 | 35 | ns | VID = -1.5 V to 1.5 V, See Figure 13 | 6 |
| Propagation delay time, high-to-low-level output | tPHL |  | 23 | 35 | ns | VID = -1.5 V to 1.5 V, See Figure 13 | 6 |
| Output enable time to high level, receiver | tPZH |  | 10 | 30 | ns | See Figure 14 | 6 |
| Output enable time to low level, receiver | tPZL |  | 12 | 30 | ns | See Figure 14 | 6 |
| Output disable time from high level, receiver | tPHZ |  | 20 | 35 | ns | See Figure 14 | 6 |
| Output disable time from low level, receiver | tPLZ |  | 17 | 25 | ns | See Figure 14 | 6 |
| Input hysteresis voltage (VIT+, VIT-) | Vhys |  | 50 |  | mV |  | 5 |
| Junction-to-ambient thermal resistance (D package, 8 pins) | RθJA |  | 172 |  | °C/W |  | 4 |

## CAD (KiCad official)

- Symbol: `XL75176AD`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `xl75176ad-etched.step` / `xl75176ad-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `xl75176ad.step` / `xl75176ad.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [XINLUDA datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603345668795097088) (16 pp, sha256 `db47aae6c7daf71b`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/xl75176ad-datasheet.pdf)