component
XL74LS32
Public Made by Adomby adom
XINLUDA Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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XL74LS32
XINLUDA · Gates · SOP-14
XL74LS32 from XINLUDA, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Gate 1 input A; output 1Y is high when either 1A or 1B is high. |
| 2 | 1B | input | Gate 1 input B; output 1Y is high when either 1A or 1B is high. |
| 3 | 1Y | output | Gate 1 output, rated IOH -0.4 mA and IOL 8 mA. |
| 4 | 2A | input | Gate 2 input A; output 2Y is high when either 2A or 2B is high. |
| 5 | 2B | input | Gate 2 input B; output 2Y is high when either 2A or 2B is high. |
| 6 | 2Y | output | Gate 2 output, rated IOH -0.4 mA and IOL 8 mA. |
| 7 | GND | power_in | Ground, the network ground reference for all voltage values. |
| 8 | 3Y | output | Gate 3 output, rated IOH -0.4 mA and IOL 8 mA. |
| 9 | 3A | input | Gate 3 input A; output 3Y is high when either 3A or 3B is high. |
| 10 | 3B | input | Gate 3 input B; output 3Y is high when either 3A or 3B is high. |
| 11 | 4Y | output | Gate 4 output, rated IOH -0.4 mA and IOL 8 mA. |
| 12 | 4A | input | Gate 4 input A; output 4Y is high when either 4A or 4B is high. |
| 13 | 4B | input | Gate 4 input B; output 4Y is high when either 4A or 4B is high. |
| 14 | VCC | power_in | Supply voltage, recommended 4.75 V to 5.25 V (5 V nominal), absolute maximum 7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | SOP-14 |
| Category | Logic ICs |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 7 | V | see Note 1 | 2 | ||
| Input voltage | VI | 7 | V | 74LS32 | 2 | ||
| Operating free-air temperature range | TA | 0 | 70 | C | SOP package | 2 | |
| Storage temperature range | Tstg | -65 | 150 | C | 2 | ||
| Supply voltage | VCC | 4.75 | 5 | 5.25 | V | 3 | |
| High-level input voltage | VIH | 2 | V | 3 | |||
| Low-level input voltage | VIL | 0.8 | V | 3 | |||
| High-level output current | IOH | -0.4 | mA | 3 | |||
| Low-level output current | IOL | 8 | mA | 3 | |||
| Operating free-air temperature | TA | 0 | 70 | C | 3 | ||
| Input clamp voltage | VIK | -1.5 | V | VCC = MIN, II = −18 mA | 3 | ||
| High-level output voltage | VOH | 2.7 | 3.4 | V | VCC = MIN, VIL = MAX, IOH = −0.4 mA | 3 | |
| Low-level output voltage | VOL | 0.25 | 0.4 | V | VCC = MIN, VIH = 2 V, IOL = 4 mA | 3 | |
| Low-level output voltage | VOL | 0.35 | 0.5 | V | VCC = MIN, VIH = 2 V, IOL = 8 mA | 3 | |
| Input current at max input voltage | II | 0.1 | mA | VCC = MAX, VI = 7 V | 3 | ||
| High-level input current | IIH | 20 | µA | VCC = MAX, VI = 2.7 V | 3 | ||
| Low-level input current | IIL | -0.4 | mA | VCC = MAX, VI = 0.4 V | 3 | ||
| Short-circuit output current | IOS | -20 | -100 | mA | VCC = MAX | 3 | |
| Supply current, outputs high | ICCH | 3.1 | 6.2 | mA | VCC = MAX, VI = 4.5 V | 3 | |
| Supply current, outputs low | ICCL | 4.9 | 9.8 | mA | VCC = MAX, VI = 0 V | 3 | |
| Propagation delay, low-to-high | tPLH | 14 | 22 | ns | A or B to Y, RL = 2 kΩ, CL = 15 pF, VCC = 5 V, TA = 25℃ | 3 | |
| Propagation delay, high-to-low | tPHL | 14 | 22 | ns | A or B to Y, RL = 2 kΩ, CL = 15 pF, VCC = 5 V, TA = 25℃ | 3 |
CAD (KiCad official)
- Symbol:
XL74LS32 - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files:
xl74ls32-etched.step/xl74ls32-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);xl74ls32.step/xl74ls32.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XINLUDA datasheet (5 pp, sha256
613634093b689243, retrieved 2026-10-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# XL74LS32
**XINLUDA** · Gates · SOP-14
XL74LS32 from XINLUDA, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Gate 1 input A; output 1Y is high when either 1A or 1B is high. |
| 2 | 1B | input | Gate 1 input B; output 1Y is high when either 1A or 1B is high. |
| 3 | 1Y | output | Gate 1 output, rated IOH -0.4 mA and IOL 8 mA. |
| 4 | 2A | input | Gate 2 input A; output 2Y is high when either 2A or 2B is high. |
| 5 | 2B | input | Gate 2 input B; output 2Y is high when either 2A or 2B is high. |
| 6 | 2Y | output | Gate 2 output, rated IOH -0.4 mA and IOL 8 mA. |
| 7 | GND | power_in | Ground, the network ground reference for all voltage values. |
| 8 | 3Y | output | Gate 3 output, rated IOH -0.4 mA and IOL 8 mA. |
| 9 | 3A | input | Gate 3 input A; output 3Y is high when either 3A or 3B is high. |
| 10 | 3B | input | Gate 3 input B; output 3Y is high when either 3A or 3B is high. |
| 11 | 4Y | output | Gate 4 output, rated IOH -0.4 mA and IOL 8 mA. |
| 12 | 4A | input | Gate 4 input A; output 4Y is high when either 4A or 4B is high. |
| 13 | 4B | input | Gate 4 input B; output 4Y is high when either 4A or 4B is high. |
| 14 | VCC | power_in | Supply voltage, recommended 4.75 V to 5.25 V (5 V nominal), absolute maximum 7 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | SOP-14 |
| Category | Logic ICs |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | | | 7 | V | see Note 1 | 2 |
| Input voltage | VI | | | 7 | V | 74LS32 | 2 |
| Operating free-air temperature range | TA | 0 | | 70 | C | SOP package | 2 |
| Storage temperature range | Tstg | -65 | | 150 | C | | 2 |
| Supply voltage | VCC | 4.75 | 5 | 5.25 | V | | 3 |
| High-level input voltage | VIH | 2 | | | V | | 3 |
| Low-level input voltage | VIL | | | 0.8 | V | | 3 |
| High-level output current | IOH | | | -0.4 | mA | | 3 |
| Low-level output current | IOL | | | 8 | mA | | 3 |
| Operating free-air temperature | TA | 0 | | 70 | C | | 3 |
| Input clamp voltage | VIK | | | -1.5 | V | VCC = MIN, II = −18 mA | 3 |
| High-level output voltage | VOH | 2.7 | 3.4 | | V | VCC = MIN, VIL = MAX, IOH = −0.4 mA | 3 |
| Low-level output voltage | VOL | | 0.25 | 0.4 | V | VCC = MIN, VIH = 2 V, IOL = 4 mA | 3 |
| Low-level output voltage | VOL | | 0.35 | 0.5 | V | VCC = MIN, VIH = 2 V, IOL = 8 mA | 3 |
| Input current at max input voltage | II | | | 0.1 | mA | VCC = MAX, VI = 7 V | 3 |
| High-level input current | IIH | | | 20 | µA | VCC = MAX, VI = 2.7 V | 3 |
| Low-level input current | IIL | | | -0.4 | mA | VCC = MAX, VI = 0.4 V | 3 |
| Short-circuit output current | IOS | -20 | | -100 | mA | VCC = MAX | 3 |
| Supply current, outputs high | ICCH | | 3.1 | 6.2 | mA | VCC = MAX, VI = 4.5 V | 3 |
| Supply current, outputs low | ICCL | | 4.9 | 9.8 | mA | VCC = MAX, VI = 0 V | 3 |
| Propagation delay, low-to-high | tPLH | | 14 | 22 | ns | A or B to Y, RL = 2 kΩ, CL = 15 pF, VCC = 5 V, TA = 25℃ | 3 |
| Propagation delay, high-to-low | tPHL | | 14 | 22 | ns | A or B to Y, RL = 2 kΩ, CL = 15 pF, VCC = 5 V, TA = 25℃ | 3 |
## CAD (KiCad official)
- Symbol: `XL74LS32`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files: `xl74ls32-etched.step` / `xl74ls32-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `xl74ls32.step` / `xl74ls32.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [XINLUDA datasheet](docs/xl74ls32-datasheet.pdf) (5 pp, sha256 `613634093b689243`, retrieved 2026-10-22, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/xl74ls32-datasheet.pdf)