# XL74LS30

**XINLUDA** · Logic Gates · SOP-14

XL74LS30 from XINLUDA, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Gate input A of the 8-input NAND gate; output Y is low only when all inputs are high. |
| 2 | B | input | Gate input B of the 8-input NAND gate; output Y is low only when all inputs are high. |
| 3 | C | input | Gate input C of the 8-input NAND gate; output Y is low only when all inputs are high. |
| 4 | D | input | Gate input D of the 8-input NAND gate; output Y is low only when all inputs are high. |
| 5 | E | input | Gate input E of the 8-input NAND gate; output Y is low only when all inputs are high. |
| 6 | F | input | Gate input F of the 8-input NAND gate; output Y is low only when all inputs are high. |
| 7 | GND | power_in | Ground pin, the network ground terminal that supply voltage values are referenced to. |
| 8 | Y | output | NAND gate output, low when all inputs are high and high when one or more inputs are low; IOH -0.4 mA max, IOL 8 mA max. |
| 9 | NC | unconnected | No internal connection. |
| 10 | NC | unconnected | No internal connection. |
| 11 | G | input | Gate input G of the 8-input NAND gate; output Y is low only when all inputs are high. |
| 12 | H | input | Gate input H of the 8-input NAND gate; output Y is low only when all inputs are high. |
| 13 | NC | unconnected | No internal connection. |
| 14 | VCC | power_in | Supply voltage pin, recommended 4.75 V to 5.25 V (5 V nominal), absolute maximum 7 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 4.75 | 5 | 5.25 | V |  | 3 |
| High-level input voltage | VIH | 2 |  |  | V |  | 3 |
| Low-level input voltage | VIL |  |  | 0.8 | V |  | 3 |
| High-level output current | IOH |  |  | -0.4 | mA |  | 3 |
| Low-level output current | IOL |  |  | 8 | mA |  | 3 |
| Operating free-air temperature | TA | 0 |  | 70 | C |  | 3 |
| Supply voltage | VCC |  |  | 7 | V | Voltage values are with respect to network ground terminal (Note 1) | 2 |
| Input voltage (74LS30) | VI |  |  | 7 | V | 74LS30 | 2 |
| Operating free-air temperature range (SOP package) | TA | 0 |  | 70 | C | SOP package | 2 |
| Storage temperature range | Tstg | -65 |  | 150 | C |  | 2 |
| Input clamp voltage | VIK |  |  | -1.5 | V | VCC = MIN, II = −18 mA | 3 |
| High-level output voltage | VOH | 2.7 | 3.4 |  | V | VCC = MIN, VIL = MAX, IOH = −0.4 mA | 3 |
| Low-level output voltage | VOL |  |  | 0.4 | V | VCC = MIN, VIH = 2 V, IOL = 4 mA | 3 |
| Low-level output voltage | VOL |  | 0.25 | 0.5 | V | VCC = MIN, VIH = 2 V, IOL = 8 mA | 3 |
| Input current at maximum input voltage | II |  |  | 0.1 | mA | VCC = MAX, VI = 7 V | 3 |
| High-level input current | IIH |  |  | 20 | µA | VCC = MAX, VI = 2.7 V | 3 |
| Low-level input current | IIL |  |  | -0.4 | mA | VCC = MAX, VI = 0.4 V | 3 |
| Short-circuit output current | IOS | -20 |  | -100 | mA | VCC = MAX | 3 |
| Supply current, outputs high | ICCH |  | 0.35 | 0.5 | mA | VCC = MAX, VI = 4.5 V | 3 |
| Supply current, outputs low | ICCL |  | 0.6 | 1.1 | mA | VCC = MAX, VI = 0 V | 3 |
| Propagation delay time, low-to-high-level output | tPLH |  | 8 | 15 | ns | RL = 2 kΩ, CL = 15 pF (VCC = 5 V, TA = 25°C per section heading) | 3 |
| Propagation delay time, high-to-low-level output | tPHL |  | 13 | 20 | ns | RL = 2 kΩ, CL = 15 pF (VCC = 5 V, TA = 25°C per section heading) | 3 |

## CAD (KiCad official)

- Symbol: `XL74LS30`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files: `xl74ls30-etched.step` / `xl74ls30-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `xl74ls30.step` / `xl74ls30.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [XINLUDA datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588906343654150144) (5 pp, sha256 `f328380595317567`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/xl74ls30-datasheet.pdf)