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XL74LS20

Public Made by Adom

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XINLUDA Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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XL74LS20

XINLUDA · Gates · SOP-14

XL74LS20 from XINLUDA, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Gate 1 input A of the 4-input NAND; high-level input minimum 2 V, low-level maximum 0.8 V.
2 1B input Gate 1 input B of the 4-input NAND; high-level input minimum 2 V, low-level maximum 0.8 V.
3 NC unconnected No internal connection.
4 1C input Gate 1 input C of the 4-input NAND; high-level input minimum 2 V, low-level maximum 0.8 V.
5 1D input Gate 1 input D of the 4-input NAND; high-level input minimum 2 V, low-level maximum 0.8 V.
6 1Y output Gate 1 output, low only when all four inputs are high; IOH -0.4 mA and IOL 8 mA maximum.
7 GND power_in Ground, the reference for all voltage values.
8 2Y output Gate 2 output, low only when all four inputs are high; IOH -0.4 mA and IOL 8 mA maximum.
9 2A input Gate 2 input A of the 4-input NAND; high-level input minimum 2 V, low-level maximum 0.8 V.
10 2B input Gate 2 input B of the 4-input NAND; high-level input minimum 2 V, low-level maximum 0.8 V.
11 NC unconnected No internal connection.
12 2C input Gate 2 input C of the 4-input NAND; high-level input minimum 2 V, low-level maximum 0.8 V.
13 2D input Gate 2 input D of the 4-input NAND; high-level input minimum 2 V, low-level maximum 0.8 V.
14 VCC power_in Supply voltage, recommended 4.75 V to 5.25 V (5 V nominal), absolute maximum 7 V.

Key specifications

Parameter Value
Manufacturer XINLUDA
Package SOP-14
Category Logic ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 4.75 5 5.25 V 4
High-level input voltage VIH 2 V 4
Low-level input voltage VIL 0.8 V 4
High-level output current IOH -0.4 mA 4
Low-level output current IOL 8 mA 4
Operating free-air temperature TA 0 70 C 4
Input clamp voltage VIK -1.5 V VCC = MIN, II = −18 mA 4
High-level output voltage VOH 2.7 3.4 V VCC = MIN, VIL = MAX, IOH = −0.4 mA 4
Low-level output voltage VOL 0.4 V VCC = MIN, VIH = 2 V, IOL = 4 mA 4
Low-level output voltage VOL 0.25 0.5 V VCC = MIN, VIH = 2 V, IOL = 8 mA 4
Input current at max input voltage II 0.1 mA VCC = MAX, VI = 7 V 4
High-level input current IIH 20 µA VCC = MAX, VI = 2.7 V 4
Low-level input current IIL -0.4 mA VCC = MAX, VI = 0.4 V 4
Short-circuit output current IOS -20 -100 mA VCC = MAX 4
Supply current, outputs high ICCH 0.4 0.8 mA VCC = MAX, VI = 4.5 V 4
Supply current, outputs low ICCL 1.2 2.2 mA VCC = MAX, VI = 0 V 4
Propagation delay, low-to-high tPLH 9 15 ns VCC = 5 V, TA = 25 C, RL = 2 kΩ, CL = 15 pF 4
Propagation delay, high-to-low tPHL 10 15 ns VCC = 5 V, TA = 25 C, RL = 2 kΩ, CL = 15 pF 4
Supply voltage VCC 7 V 3
Input voltage VI 7 V 74LS20 3
Operating free-air temperature range 0 70 C SOP package 3
Storage temperature range Tstg -65 150 C 3

CAD (KiCad official)

  • Symbol: XL74LS20
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: xl74ls20-etched.step / xl74ls20-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xl74ls20.step / xl74ls20.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (6 pp, sha256 959424f1244ba473, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF