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xl74ls08: factory component page (tier=lcsc)

Ray ·679dd73b85 ·1mo ago ·parent 060c8ef
1 file changed +162−8
page.json+162−8
@@ -1,13 +1,172 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "xl74ls08",+  "title": "XL74LS08",+  "brief": "XINLUDA Gates, SOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "version": "0.1.0",-  "type": "component",-  "description": "XINLUDA Gates, SOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "logic",     "xl74ls08"   ],+  "component": {+    "mpn": "XL74LS08",+    "manufacturer": "XINLUDA",+    "package": "SOP-14",+    "pin_count": 14,+    "category": "Logic",+    "subcategory": "Gates",+    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/34cf99fd2a534ec08e0ac6b8bcb72ec2.pdf",+    "parts": {+      "symbol": "xl74ls08.kicad_sym",+      "footprint": "xl74ls08.kicad_mod",+      "model_3d": "xl74ls08.glb",+      "model_3d_step": "xl74ls08.step",+      "lbr": "xl74ls08.lbr"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "1A",+        "type": "input",+        "description": "Gate 1, input A. TTL-compatible logic input (VIH \u2265 2 V, VIL \u2264 0.8 V)."+      },+      {+        "number": "2",+        "name": "1B",+        "type": "input",+        "description": "Gate 1, input B. TTL-compatible logic input (VIH \u2265 2 V, VIL \u2264 0.8 V)."+      },+      {+        "number": "3",+        "name": "1Y",+        "type": "output",+        "description": "Gate 1 output. Y = 1A AND 1B. IOH = -0.4 mA, IOL = 8 mA."+      },+      {+        "number": "4",+        "name": "2A",+        "type": "input",+        "description": "Gate 2, input A. TTL-compatible logic input (VIH \u2265 2 V, VIL \u2264 0.8 V)."+      },+      {+        "number": "5",+        "name": "2B",+        "type": "input",+        "description": "Gate 2, input B. TTL-compatible logic input (VIH \u2265 2 V, VIL \u2264 0.8 V)."+      },+      {+        "number": "6",+        "name": "2Y",+        "type": "output",+        "description": "Gate 2 output. Y = 2A AND 2B. IOH = -0.4 mA, IOL = 8 mA."+      },+      {+        "number": "7",+        "name": "GND",+        "type": "power_in",+        "description": "Ground reference (0 V)."+      },+      {+        "number": "8",+        "name": "3Y",+        "type": "output",+        "description": "Gate 3 output. Y = 3A AND 3B. IOH = -0.4 mA, IOL = 8 mA."+      },+      {+        "number": "9",+        "name": "3A",+        "type": "input",+        "description": "Gate 3, input A. TTL-compatible logic input (VIH \u2265 2 V, VIL \u2264 0.8 V)."+      },+      {+        "number": "10",+        "name": "3B",+        "type": "input",+        "description": "Gate 3, input B. TTL-compatible logic input (VIH \u2265 2 V, VIL \u2264 0.8 V)."+      },+      {+        "number": "11",+        "name": "4Y",+        "type": "output",+        "description": "Gate 4 output. Y = 4A AND 4B. IOH = -0.4 mA, IOL = 8 mA."+      },+      {+        "number": "12",+        "name": "4A",+        "type": "input",+        "description": "Gate 4, input A. TTL-compatible logic input (VIH \u2265 2 V, VIL \u2264 0.8 V)."+      },+      {+        "number": "13",+        "name": "4B",+        "type": "input",+        "description": "Gate 4, input B. TTL-compatible logic input (VIH \u2265 2 V, VIL \u2264 0.8 V)."+      },+      {+        "number": "14",+        "name": "VCC",+        "type": "power_in",+        "description": "Positive supply voltage. Recommended 4.75-5.25 V (5 V nominal), absolute max 7 V."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://datasheet.lcsc.com/datasheet/pdf/34cf99fd2a534ec08e0ac6b8bcb72ec2.pdf",+        "pages": 5,+        "sha256": "e46ba5a1c45d414d",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 14,+        "described": 14,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Manufacturer": "XINLUDA",+      "Package": "SOP-14",+      "Category": "Logic",+      "Pins": "14"+    }+  },+  "variants": [+    {+      "mpn": "XL74LS08",+      "kind": "packaging"+    },+    {+      "mpn": "XL74LS08XD74LS08",+      "kind": "packaging"+    }+  ],+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "xl74ls08"+  ],+  "discovery_pitch": "XL74LS08 (XINLUDA) component page with datasheet-verified CAD.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -25,10 +184,5 @@     "docs/xl74ls08-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file