component
XL74LS08
Public Made by Adomby adom
XINLUDA Gates, SOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+12−9@@ -32,13 +32,13 @@ "number": "1", "name": "1A", "type": "input",- "description": "Gate 1, input A. TTL-compatible logic input (VIH \u2265 2 V, VIL \u2264 0.8 V)."+ "description": "Gate 1, input A. TTL-compatible logic input (VIH ≥ 2 V, VIL ≤ 0.8 V)." }, { "number": "2", "name": "1B", "type": "input",- "description": "Gate 1, input B. TTL-compatible logic input (VIH \u2265 2 V, VIL \u2264 0.8 V)."+ "description": "Gate 1, input B. TTL-compatible logic input (VIH ≥ 2 V, VIL ≤ 0.8 V)." }, { "number": "3",@@ -50,13 +50,13 @@ "number": "4", "name": "2A", "type": "input",- "description": "Gate 2, input A. TTL-compatible logic input (VIH \u2265 2 V, VIL \u2264 0.8 V)."+ "description": "Gate 2, input A. TTL-compatible logic input (VIH ≥ 2 V, VIL ≤ 0.8 V)." }, { "number": "5", "name": "2B", "type": "input",- "description": "Gate 2, input B. TTL-compatible logic input (VIH \u2265 2 V, VIL \u2264 0.8 V)."+ "description": "Gate 2, input B. TTL-compatible logic input (VIH ≥ 2 V, VIL ≤ 0.8 V)." }, { "number": "6",@@ -80,13 +80,13 @@ "number": "9", "name": "3A", "type": "input",- "description": "Gate 3, input A. TTL-compatible logic input (VIH \u2265 2 V, VIL \u2264 0.8 V)."+ "description": "Gate 3, input A. TTL-compatible logic input (VIH ≥ 2 V, VIL ≤ 0.8 V)." }, { "number": "10", "name": "3B", "type": "input",- "description": "Gate 3, input B. TTL-compatible logic input (VIH \u2265 2 V, VIL \u2264 0.8 V)."+ "description": "Gate 3, input B. TTL-compatible logic input (VIH ≥ 2 V, VIL ≤ 0.8 V)." }, { "number": "11",@@ -98,13 +98,13 @@ "number": "12", "name": "4A", "type": "input",- "description": "Gate 4, input A. TTL-compatible logic input (VIH \u2265 2 V, VIL \u2264 0.8 V)."+ "description": "Gate 4, input A. TTL-compatible logic input (VIH ≥ 2 V, VIL ≤ 0.8 V)." }, { "number": "13", "name": "4B", "type": "input",- "description": "Gate 4, input B. TTL-compatible logic input (VIH \u2265 2 V, VIL \u2264 0.8 V)."+ "description": "Gate 4, input B. TTL-compatible logic input (VIH ≥ 2 V, VIL ≤ 0.8 V)." }, { "number": "14",@@ -184,5 +184,8 @@ "docs/xl74ls08-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ]+ ],+ "visibility": {+ "public": true+ } }