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docs xl74hc165: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 4d ago
viewers xl74hc165: viewers · Ray 1mo ago
package.json Publish 0.2.0 · Ray 1mo ago
page.json Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout") · Ray 11d ago
README.md xl74hc165: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 17d ago
xl74hc165-etched.fit.json xl74hc165: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 4d ago
xl74hc165-etched.glb xl74hc165: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 4d ago
xl74hc165-etched.step xl74hc165: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 4d ago
xl74hc165.glb Publish 0.1.0 · Ray 1mo ago
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xl74hc165.step Publish 0.1.0 · Ray 1mo ago

XL74HC165

XINLUDA · Shifting Register · SOP-16

XL74HC165 from XINLUDA, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 /PL input Asynchronous parallel load input (active LOW). When LOW, data on D0-D7 is loaded into the shift register asynchronously.
2 CP input Clock input, LOW-to-HIGH edge-triggered. Shifts serial data on rising edges when /CE is LOW and /PL is HIGH.
3 D4 input Parallel data input bit 4. Loaded into the shift register on /PL LOW.
4 D5 input Parallel data input bit 5. Loaded into the shift register on /PL LOW.
5 D6 input Parallel data input bit 6. Loaded into the shift register on /PL LOW.
6 D7 input Parallel data input bit 7 (MSB, appears first at Q7). Loaded into the shift register on /PL LOW.
7 /Q7 output Complementary serial output from the last stage (inverted Q7).
8 GND power_in Ground reference, 0 V.
9 Q7 output Serial output from the last stage of the shift register.
10 DS input Serial data input. Data entering the register serially on each LOW-to-HIGH CP transition when /PL is HIGH and /CE is LOW.
11 D0 input Parallel data input bit 0. Loaded into the shift register on /PL LOW.
12 D1 input Parallel data input bit 1. Loaded into the shift register on /PL LOW.
13 D2 input Parallel data input bit 2. Loaded into the shift register on /PL LOW.
14 D3 input Parallel data input bit 3. Loaded into the shift register on /PL LOW.
15 /CE input Clock enable input (active LOW). When LOW, CP is enabled; when HIGH, the CP input is disabled (hold).
16 VCC power_in Positive supply voltage, 2.0 V to 6.0 V (recommended).

Key specifications

Parameter Value
Manufacturer XINLUDA
Package SOP-16
Category Logic
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • XL74HC165
  • XL74HC165-TS
  • XL74HC165XD74HC165

CAD (KiCad official)

  • Symbol: XL74HC165
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: xl74hc165-etched.step / xl74hc165-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xl74hc165.step / xl74hc165.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
xl74hc165.step 217 KB You want the bare part, or you mark your own boards.
xl74hc165-etched.step 2.0 MB You want the part with XL74HC165 already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 518 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (13 pp, sha256 79f2636f72dd59f5, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF