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XL74C923

Public Made by Adom

by adom

XINLUDA Signal Switches, Multiplexers, Decoders, SOIC-20-300mil. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.

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XL74C923

XINLUDA · Signal Switches, Multiplexers, Decoders · SOIC-20-300mil

XL74C923 from XINLUDA, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ROW Y1 input Row input Y1 of the key matrix with an on-chip pull-up that permits switches up to 50 kΩ on-resistance.
2 ROW Y2 input Row input Y2 of the key matrix with an on-chip pull-up that permits switches up to 50 kΩ on-resistance.
3 ROW Y3 input Row input Y3 of the key matrix with an on-chip pull-up that permits switches up to 50 kΩ on-resistance.
4 ROW Y4 input Row input Y4 of the key matrix with an on-chip pull-up that permits switches up to 50 kΩ on-resistance.
5 ROW Y5 input Row input Y5 of the key matrix (fifth row of the 20-key array) with an on-chip pull-up.
6 OSCILLATOR input Keyboard scan oscillator input, driven by an external clock or set by an external capacitor (COSC) that controls the scan rate.
7 KEYBOUNCE MASK passive Connection for the single external key bounce mask capacitor (CMSK) that sets the debounce period; omitting the capacitor defeats debounce.
8 COLUMN X4 output Open-drain column scan output X4 that sequentially outputs a logic 0 (low 25% of the time, otherwise off).
9 COLUMN X3 output Open-drain column scan output X3 that sequentially outputs a logic 0 (low 25% of the time, otherwise off).
10 GND power_in Ground.
11 COLUMN X2 output Open-drain column scan output X2 that sequentially outputs a logic 0 (low 25% of the time, otherwise off).
12 COLUMN X1 output Open-drain column scan output X1 that sequentially outputs a logic 0 (low 25% of the time, otherwise off).
13 DATA AVAILABLE output Goes high when a valid keyboard entry has been made and returns low when the key is released.
14 OUTPUT ENABLE input Active-low output enable; taking it low enables the 3-STATE data outputs.
15 DATA OUT E tri_state 3-STATE encoded key code output bit E, LPTTL compatible, held by the last key register.
16 DATA OUT D tri_state 3-STATE encoded key code output bit D, LPTTL compatible, held by the last key register.
17 DATA OUT C tri_state 3-STATE encoded key code output bit C, LPTTL compatible, held by the last key register.
18 DATA OUT B tri_state 3-STATE encoded key code output bit B, LPTTL compatible, held by the last key register.
19 DATA OUT A tri_state 3-STATE encoded key code output bit A, LPTTL compatible, held by the last key register.
20 VCC power_in Positive supply, operating range 3V to 15V, absolute maximum 18V.

Key specifications

Parameter Value
Manufacturer XINLUDA
Package SOIC-20-300mil
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Positive-Going Threshold Voltage at Osc and KBM Inputs VT 3 3.6 4.3 V VCC=5V, IIN=0.7mA 4
Positive-Going Threshold Voltage at Osc and KBM Inputs VT 6 6.8 8.6 V VCC=10V, IIN=1.4mA 4
Positive-Going Threshold Voltage at Osc and KBM Inputs VT 9 10 12.9 V VCC=15V, IIN=2.1mA 4
Negative-Going Threshold Voltage at Osc and KBM Inputs VT 0.7 1.4 2 V VCC=5V, IIN=0.7mA 4
Negative-Going Threshold Voltage at Osc and KBM Inputs VT 1.4 3.2 4 V VCC=10V, IIN=1.4mA 4
Negative-Going Threshold Voltage at Osc and KBM Inputs VT 2.1 5 6 V VCC=15V, IIN=2.1mA 4
Logical 1 Input Voltage, except Osc and KBM Inputs VIN(1) 3.5 4.5 V VCC=5V 4
Logical 1 Input Voltage, except Osc and KBM Inputs VIN(1) 8 9 V VCC=10V 4
Logical 1 Input Voltage, except Osc and KBM Inputs VIN(1) 12.5 13.5 V VCC=15V 4
Logical 0 Input Voltage, except Osc and KBM Inputs VIN(0) 0.5 1.5 V VCC=5V 4
Logical 0 Input Voltage, except Osc and KBM Inputs VIN(0) 1 2 V VCC=10V 4
Logical 0 Input Voltage, except Osc and KBM Inputs VIN(0) 1.5 2.5 V VCC=15V 4
Row Pull-Up Current at Y1, Y2, Y3, Y4 and Y5 Inputs Irp 2 10 22 uA VCC=5V, VIN=0.1 VCC 4
Logical 1 Output Voltage VOUT(1) 4.5 V VCC=5V, IO=10 uA 4
Logical 1 Output Voltage VOUT(1) 9 V VCC=10V, IO=10 uA 4
Logical 1 Output Voltage VOUT(1) 13.5 V VCC=15V, IO=10 uA 4
Logical 0 Output Voltage VOUT(0) 0.5 V VCC=5V, IO=10 uA 4
Logical 0 Output Voltage VOUT(0) 1 V VCC=10V, IO=10 uA 4
Logical 0 Output Voltage VOUT(0) 1.5 V VCC=15V, IO=10 uA 4
Column ON Resistance at X1, X2, X3 and X4 Outputs Ron 500 1400 Ω VCC=5V, VO=0.5V 4
Column ON Resistance at X1, X2, X3 and X4 Outputs Ron 300 700 Ω VCC=10V, VO=1V 4
Column ON Resistance at X1, X2, X3 and X4 Outputs Ron 200 500 Ω VCC=15V, VO=1.5V 4
Supply Current Osc at 0V (one Y low) ICC 0.55 1.1 mA VCC=5V, Osc at 0V, one Y low 4
Supply Current Osc at 0V (one Y low) ICC 1.1 1.9 mA VCC=10V, Osc at 0V, one Y low 4
Supply Current Osc at 0V (one Y low) ICC 1.7 2.6 mA VCC=15V, Osc at 0V, one Y low 4
Logical 1 Input Current at Output Enable IIN(1) 0.005 1 uA VCC=15V, VIN=15V 4
Logical 0 Input Current at Output Enable IIN(0) 0.005 1 uA VCC=15V, VIN=0V 4
Logical 0 Input Voltage, CMOS/LPTTL interface, except Osc and KBM Inputs VIN(0) 0.8 V VCC=4.75V 4
Logical 1 Output Voltage, CMOS/LPTTL interface VOUT(1) 2.4 V IO=360 uA, VCC=4.75V 4
Logical 0 Output Voltage, CMOS/LPTTL interface VOUT(0) 0.4 V IO=360 uA, VCC=4.75V 5
Output Source Current (P-Channel) ISOURCE 1.75 3.3 mA VCC=5V, VOUT=0V, TA=25C 5
Output Source Current (P-Channel) ISOURCE 8 15 mA VCC=10V, VOUT=0V, TA=25C 5
Output Sink Current (N-Channel) ISINK 1.75 3.6 mA VCC=5V, VOUT=VCC, TA=25C 5
Output Sink Current (N-Channel) ISINK 8 16 mA VCC=10V, VOUT=VCC, TA=25C 5
Propagation Delay Time to Logical 0 or Logical 1 from D.A. tpd0, tpd1 60 150 ns CL=50 pF (Figure 1), VCC=5V 5
Propagation Delay Time to Logical 0 or Logical 1 from D.A. tpd0, tpd1 35 80 ns CL=50 pF (Figure 1), VCC=10V 5
Propagation Delay Time to Logical 0 or Logical 1 from D.A. tpd0, tpd1 25 60 ns CL=50 pF (Figure 1), VCC=15V 5
Propagation Delay Time from Logical 0 or Logical 1 into High Impedance State t0H, t1H 80 200 ns RL=10k, CL=10 pF (Figure 2), VCC=5V 5
Propagation Delay Time from Logical 0 or Logical 1 into High Impedance State t0H, t1H 65 150 ns RL=10k, CL=10 pF (Figure 2), VCC=10V 5
Propagation Delay Time from Logical 0 or Logical 1 into High Impedance State t0H, t1H 50 110 ns RL=10k, CL=10 pF (Figure 2), VCC=15V 5
Propagation Delay Time from High Impedance State to Logical 0 or Logical 1 tH0, tH1 100 250 ns RL=10k, CL=50 pF (Figure 2), VCC=5V 5
Propagation Delay Time from High Impedance State to Logical 0 or Logical 1 tH0, tH1 55 125 ns RL=10k, CL=50 pF (Figure 2), VCC=10V 5
Propagation Delay Time from High Impedance State to Logical 0 or Logical 1 tH0, tH1 40 90 ns RL=10k, CL=50 pF (Figure 2), VCC=15V 5
Input Capacitance CIN 5 7.5 pF Any input (Note 4) 5
Operating VCC Range VCC 3 15 V 4
Operating Temperature Range -40 85 °C 4
Supply Voltage (absolute maximum) VCC 18 V 4
Power Dissipation (PD), Small Outline PD 500 mW Small Outline package 4
Storage Temperature Range -65 150 °C 4
Lead Temperature 260 °C Soldering, 10 seconds 4

CAD (KiCad official)

  • Symbol: XL74C923
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: xl74c923-etched.step / xl74c923-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xl74c923.step / xl74c923.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (11 pp, sha256 5a5db127be601c00, retrieved 2026-10-21, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF