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XL74C922
Public Made by Adomby adom
XINLUDA Signal Switches, Multiplexers, Decoders, SOIC-20-300mil. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.
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XL74C922
XINLUDA · Signal Switches, Multiplexers, Decoders · SOIC-20-300mil
XL74C922 from XINLUDA, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ROW Y1 | input | Row 1 input of the 4x4 key matrix, with an on-chip pull-up that permits switches up to 50 kΩ on resistance. |
| 2 | ROW Y2 | input | Row 2 input of the key matrix, with an on-chip pull-up device. |
| 3 | ROW Y3 | input | Row 3 input of the key matrix, with an on-chip pull-up device. |
| 4 | ROW Y4 | input | Row 4 input of the key matrix, with an on-chip pull-up device. |
| 5 | NC | unconnected | No connection on the XL74C922 SOP package (this is the Row Y5 pin on the XL74C923). |
| 6 | OSCILLATOR | input | Schmitt-trigger oscillator input that sets the keyboard column scan rate, driven by an external clock or an external capacitor (COSC). |
| 7 | KEYBOUNCE MASK | passive | Connects the external key bounce mask capacitor (CMSK) that sets the debounce period; omitting the capacitor defeats debounce. |
| 8 | COLUMN X4 | output | Column 4 open-drain scan output that sequentially outputs a logic 0, with ON resistance of 500 Ω typ at VCC = 5 V. |
| 9 | COLUMN X3 | output | Column 3 open-drain scan output that sequentially outputs a logic 0. |
| 10 | GND | power_in | Ground reference for the device. |
| 11 | COLUMN X2 | output | Column 2 open-drain scan output that sequentially outputs a logic 0. |
| 12 | COLUMN X1 | output | Column 1 open-drain scan output that sequentially outputs a logic 0. |
| 13 | DATA AVAILABLE | output | Goes high when a valid keyboard entry has been made and returns low when the key is released. |
| 14 | OUTPUT ENABLE | input | Active-low output enable that turns on the 3-STATE data outputs when taken low. |
| 15 | NC | unconnected | No connection on the XL74C922 SOP package (this is the Data Out E pin on the XL74C923). |
| 16 | DATA OUT D | tri_state | 3-STATE LPTTL-compatible encoded key data output D from the last-key register. |
| 17 | DATA OUT C | tri_state | 3-STATE LPTTL-compatible encoded key data output C from the last-key register. |
| 18 | DATA OUT B | tri_state | 3-STATE LPTTL-compatible encoded key data output B from the last-key register. |
| 19 | DATA OUT A | tri_state | 3-STATE LPTTL-compatible encoded key data output A from the last-key register. |
| 20 | VCC | power_in | Positive supply, operating range 3 V to 15 V with an absolute maximum of 18 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | SOIC-20-300mil |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Positive-going threshold voltage at Osc and KBM inputs (VCC=5V) | VT | 3 | 3.6 | 4.3 | V | VCC=5V, IIN=0.7mA | 4 |
| Positive-going threshold voltage at Osc and KBM inputs (VCC=10V) | VT | 6 | 6.8 | 8.6 | V | VCC=10V, IIN=1.4mA | 4 |
| Positive-going threshold voltage at Osc and KBM inputs (VCC=15V) | VT | 9 | 10 | 12.9 | V | VCC=15V, IIN=2.1mA | 4 |
| Negative-going threshold voltage at Osc and KBM inputs (VCC=5V) | VT | 0.7 | 1.4 | 2 | V | VCC=5V, IIN=0.7mA | 4 |
| Negative-going threshold voltage at Osc and KBM inputs (VCC=10V) | VT | 1.4 | 3.2 | 4 | V | VCC=10V, IIN=1.4mA | 4 |
| Negative-going threshold voltage at Osc and KBM inputs (VCC=15V) | VT | 2.1 | 5 | 6 | V | VCC=15V, IIN=2.1mA | 4 |
| Logical 1 input voltage, except Osc and KBM inputs (VCC=5V) | VIN(1) | 3.5 | 4.5 | V | VCC=5V | 4 | |
| Logical 1 input voltage, except Osc and KBM inputs (VCC=10V) | VIN(1) | 8 | 9 | V | VCC=10V | 4 | |
| Logical 1 input voltage, except Osc and KBM inputs (VCC=15V) | VIN(1) | 12.5 | 13.5 | V | VCC=15V | 4 | |
| Logical 0 input voltage, except Osc and KBM inputs (VCC=5V) | VIN(0) | 0.5 | 1.5 | V | VCC=5V | 4 | |
| Logical 0 input voltage, except Osc and KBM inputs (VCC=10V) | VIN(0) | 1 | 2 | V | VCC=10V | 4 | |
| Logical 0 input voltage, except Osc and KBM inputs (VCC=15V) | VIN(0) | 1.5 | 2.5 | V | VCC=15V | 4 | |
| Row pull-up current at Y1-Y5 inputs (VCC=5V) | Irp | 2 | 5 | µA | VIN=0.1VCC, VCC=5V | 4 | |
| Row pull-up current at Y1-Y5 inputs (VCC=10V) | Irp | 10 | 20 | µA | VIN=0.1VCC, VCC=10V | 4 | |
| Row pull-up current at Y1-Y5 inputs (VCC=15V) | Irp | 22 | 45 | µA | VIN=0.1VCC, VCC=15V | 4 | |
| Logical 1 output voltage (VCC=5V) | VOUT(1) | 4.5 | V | VCC=5V, IO=10µA | 4 | ||
| Logical 1 output voltage (VCC=10V) | VOUT(1) | 9 | V | VCC=10V, IO=10µA | 4 | ||
| Logical 1 output voltage (VCC=15V) | VOUT(1) | 13.5 | V | VCC=15V, IO=10µA | 4 | ||
| Logical 0 output voltage (VCC=5V) | VOUT(0) | 0.5 | V | VCC=5V, IO=10µA | 4 | ||
| Logical 0 output voltage (VCC=10V) | VOUT(0) | 1 | V | VCC=10V, IO=10µA | 4 | ||
| Logical 0 output voltage (VCC=15V) | VOUT(0) | 1.5 | V | VCC=15V, IO=10µA | 4 | ||
| Column ON resistance at X1-X4 outputs (VCC=5V) | Ron | 500 | 1400 | Ω | VCC=5V, VO=0.5V | 4 | |
| Column ON resistance at X1-X4 outputs (VCC=10V) | Ron | 300 | 700 | Ω | VCC=10V, VO=1V | 4 | |
| Column ON resistance at X1-X4 outputs (VCC=15V) | Ron | 200 | 500 | Ω | VCC=15V, VO=1.5V | 4 | |
| Supply current, Osc at 0V (one Y low) (VCC=5V) | ICC | 0.55 | 1.1 | mA | Osc at 0V, one Y low, VCC=5V | 4 | |
| Supply current, Osc at 0V (one Y low) (VCC=10V) | ICC | 1.1 | 1.9 | mA | Osc at 0V, one Y low, VCC=10V | 4 | |
| Supply current, Osc at 0V (one Y low) (VCC=15V) | ICC | 1.7 | 2.6 | mA | Osc at 0V, one Y low, VCC=15V | 4 | |
| Logical 1 input current at output enable | IIN(1) | 0.005 | 1 | µA | VCC=15V, VIN=15V | 4 | |
| Logical 0 input current at output enable | IIN(0) | 0.005 | 1 | µA | VCC=15V, VIN=0V | 4 | |
| Logical 0 input voltage, CMOS/LPTTL interface (except Osc and KBM inputs) | VIN(0) | 0.8 | V | VCC=4.75V | 4 | ||
| Logical 1 output voltage, CMOS/LPTTL interface | VOUT(1) | 2.4 | V | IO=360µA, VCC=4.75V | 4 | ||
| Logical 0 output voltage, CMOS/LPTTL interface | VOUT(0) | 0.4 | V | IO=360µA, VCC=4.75V | 5 | ||
| Output source current, P-channel (VCC=5V) | ISOURCE | 1.75 | 3.3 | mA | VCC=5V, VOUT=0V, TA=25°C | 5 | |
| Output source current, P-channel (VCC=10V) | ISOURCE | 8 | 15 | mA | VCC=10V, VOUT=0V, TA=25°C | 5 | |
| Output sink current, N-channel (VCC=5V) | ISINK | 1.75 | 3.6 | mA | VCC=5V, VOUT=VCC, TA=25°C | 5 | |
| Output sink current, N-channel (VCC=10V) | ISINK | 8 | 16 | mA | VCC=10V, VOUT=VCC, TA=25°C | 5 | |
| Propagation delay to logical 0 or 1 from D.A. (VCC=5V) | tpd0, tpd1 | 60 | 150 | ns | CL=50pF (Figure 1) | 5 | |
| Propagation delay to logical 0 or 1 from D.A. (VCC=10V) | tpd0, tpd1 | 35 | 80 | ns | CL=50pF (Figure 1) | 5 | |
| Propagation delay to logical 0 or 1 from D.A. (VCC=15V) | tpd0, tpd1 | 25 | 60 | ns | CL=50pF (Figure 1) | 5 | |
| Propagation delay into high impedance state (VCC=5V) | t0H, t1H | 80 | 200 | ns | RL=10k, CL=10pF (Figure 2), VCC=5V | 5 | |
| Propagation delay into high impedance state (VCC=10V) | t0H, t1H | 65 | 150 | ns | RL=10k, CL=10pF (Figure 2), VCC=10V | 5 | |
| Propagation delay into high impedance state (VCC=15V) | t0H, t1H | 50 | 110 | ns | RL=10k, CL=10pF (Figure 2), VCC=15V | 5 | |
| Propagation delay from high impedance state (VCC=5V) | tH0, tH1 | 100 | 250 | ns | RL=10k, CL=50pF (Figure 2), VCC=5V | 5 | |
| Propagation delay from high impedance state (VCC=10V) | tH0, tH1 | 55 | 125 | ns | RL=10k, CL=50pF (Figure 2), VCC=10V | 5 | |
| Propagation delay from high impedance state (VCC=15V) | tH0, tH1 | 40 | 90 | ns | RL=10k, CL=50pF (Figure 2), VCC=15V | 5 | |
| Input capacitance | CIN | 5 | 7.5 | pF | Any input (Note 4) | 5 | |
| 3-STATE output capacitance | COUT | 10 | pF | Any output (Note 4) | 5 | ||
| Operating VCC range | VCC | 3 | 15 | V | 4 | ||
| Supply voltage, absolute maximum | VCC | 18 | V | 4 | |||
| Operating temperature range | -40 | 85 | °C | XD/XL74C922, XD/XL74C923 | 4 | ||
| Storage temperature range | -65 | 150 | °C | 4 | |||
| Power dissipation, small outline package | PD | 500 | mW | Small Outline | 4 | ||
| Lead temperature, soldering | 260 | °C | 10 seconds soldering | 4 |
CAD (KiCad official)
- Symbol:
XL74C922 - Footprint:
Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm - 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files:
xl74c922-etched.step/xl74c922-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);xl74c922.step/xl74c922.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XINLUDA datasheet (11 pp, sha256
5a5db127be601c00, retrieved 2026-10-21, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# XL74C922
**XINLUDA** · Signal Switches, Multiplexers, Decoders · SOIC-20-300mil
XL74C922 from XINLUDA, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ROW Y1 | input | Row 1 input of the 4x4 key matrix, with an on-chip pull-up that permits switches up to 50 kΩ on resistance. |
| 2 | ROW Y2 | input | Row 2 input of the key matrix, with an on-chip pull-up device. |
| 3 | ROW Y3 | input | Row 3 input of the key matrix, with an on-chip pull-up device. |
| 4 | ROW Y4 | input | Row 4 input of the key matrix, with an on-chip pull-up device. |
| 5 | NC | unconnected | No connection on the XL74C922 SOP package (this is the Row Y5 pin on the XL74C923). |
| 6 | OSCILLATOR | input | Schmitt-trigger oscillator input that sets the keyboard column scan rate, driven by an external clock or an external capacitor (COSC). |
| 7 | KEYBOUNCE MASK | passive | Connects the external key bounce mask capacitor (CMSK) that sets the debounce period; omitting the capacitor defeats debounce. |
| 8 | COLUMN X4 | output | Column 4 open-drain scan output that sequentially outputs a logic 0, with ON resistance of 500 Ω typ at VCC = 5 V. |
| 9 | COLUMN X3 | output | Column 3 open-drain scan output that sequentially outputs a logic 0. |
| 10 | GND | power_in | Ground reference for the device. |
| 11 | COLUMN X2 | output | Column 2 open-drain scan output that sequentially outputs a logic 0. |
| 12 | COLUMN X1 | output | Column 1 open-drain scan output that sequentially outputs a logic 0. |
| 13 | DATA AVAILABLE | output | Goes high when a valid keyboard entry has been made and returns low when the key is released. |
| 14 | OUTPUT ENABLE | input | Active-low output enable that turns on the 3-STATE data outputs when taken low. |
| 15 | NC | unconnected | No connection on the XL74C922 SOP package (this is the Data Out E pin on the XL74C923). |
| 16 | DATA OUT D | tri_state | 3-STATE LPTTL-compatible encoded key data output D from the last-key register. |
| 17 | DATA OUT C | tri_state | 3-STATE LPTTL-compatible encoded key data output C from the last-key register. |
| 18 | DATA OUT B | tri_state | 3-STATE LPTTL-compatible encoded key data output B from the last-key register. |
| 19 | DATA OUT A | tri_state | 3-STATE LPTTL-compatible encoded key data output A from the last-key register. |
| 20 | VCC | power_in | Positive supply, operating range 3 V to 15 V with an absolute maximum of 18 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | SOIC-20-300mil |
| Category | Logic |
| Pins | 20 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Positive-going threshold voltage at Osc and KBM inputs (VCC=5V) | VT | 3 | 3.6 | 4.3 | V | VCC=5V, IIN=0.7mA | 4 |
| Positive-going threshold voltage at Osc and KBM inputs (VCC=10V) | VT | 6 | 6.8 | 8.6 | V | VCC=10V, IIN=1.4mA | 4 |
| Positive-going threshold voltage at Osc and KBM inputs (VCC=15V) | VT | 9 | 10 | 12.9 | V | VCC=15V, IIN=2.1mA | 4 |
| Negative-going threshold voltage at Osc and KBM inputs (VCC=5V) | VT | 0.7 | 1.4 | 2 | V | VCC=5V, IIN=0.7mA | 4 |
| Negative-going threshold voltage at Osc and KBM inputs (VCC=10V) | VT | 1.4 | 3.2 | 4 | V | VCC=10V, IIN=1.4mA | 4 |
| Negative-going threshold voltage at Osc and KBM inputs (VCC=15V) | VT | 2.1 | 5 | 6 | V | VCC=15V, IIN=2.1mA | 4 |
| Logical 1 input voltage, except Osc and KBM inputs (VCC=5V) | VIN(1) | 3.5 | | 4.5 | V | VCC=5V | 4 |
| Logical 1 input voltage, except Osc and KBM inputs (VCC=10V) | VIN(1) | 8 | | 9 | V | VCC=10V | 4 |
| Logical 1 input voltage, except Osc and KBM inputs (VCC=15V) | VIN(1) | 12.5 | | 13.5 | V | VCC=15V | 4 |
| Logical 0 input voltage, except Osc and KBM inputs (VCC=5V) | VIN(0) | 0.5 | | 1.5 | V | VCC=5V | 4 |
| Logical 0 input voltage, except Osc and KBM inputs (VCC=10V) | VIN(0) | 1 | | 2 | V | VCC=10V | 4 |
| Logical 0 input voltage, except Osc and KBM inputs (VCC=15V) | VIN(0) | 1.5 | | 2.5 | V | VCC=15V | 4 |
| Row pull-up current at Y1-Y5 inputs (VCC=5V) | Irp | 2 | | 5 | µA | VIN=0.1VCC, VCC=5V | 4 |
| Row pull-up current at Y1-Y5 inputs (VCC=10V) | Irp | 10 | | 20 | µA | VIN=0.1VCC, VCC=10V | 4 |
| Row pull-up current at Y1-Y5 inputs (VCC=15V) | Irp | 22 | | 45 | µA | VIN=0.1VCC, VCC=15V | 4 |
| Logical 1 output voltage (VCC=5V) | VOUT(1) | 4.5 | | | V | VCC=5V, IO=10µA | 4 |
| Logical 1 output voltage (VCC=10V) | VOUT(1) | 9 | | | V | VCC=10V, IO=10µA | 4 |
| Logical 1 output voltage (VCC=15V) | VOUT(1) | 13.5 | | | V | VCC=15V, IO=10µA | 4 |
| Logical 0 output voltage (VCC=5V) | VOUT(0) | | | 0.5 | V | VCC=5V, IO=10µA | 4 |
| Logical 0 output voltage (VCC=10V) | VOUT(0) | | | 1 | V | VCC=10V, IO=10µA | 4 |
| Logical 0 output voltage (VCC=15V) | VOUT(0) | | | 1.5 | V | VCC=15V, IO=10µA | 4 |
| Column ON resistance at X1-X4 outputs (VCC=5V) | Ron | 500 | | 1400 | Ω | VCC=5V, VO=0.5V | 4 |
| Column ON resistance at X1-X4 outputs (VCC=10V) | Ron | 300 | | 700 | Ω | VCC=10V, VO=1V | 4 |
| Column ON resistance at X1-X4 outputs (VCC=15V) | Ron | 200 | | 500 | Ω | VCC=15V, VO=1.5V | 4 |
| Supply current, Osc at 0V (one Y low) (VCC=5V) | ICC | 0.55 | | 1.1 | mA | Osc at 0V, one Y low, VCC=5V | 4 |
| Supply current, Osc at 0V (one Y low) (VCC=10V) | ICC | 1.1 | | 1.9 | mA | Osc at 0V, one Y low, VCC=10V | 4 |
| Supply current, Osc at 0V (one Y low) (VCC=15V) | ICC | 1.7 | | 2.6 | mA | Osc at 0V, one Y low, VCC=15V | 4 |
| Logical 1 input current at output enable | IIN(1) | 0.005 | | 1 | µA | VCC=15V, VIN=15V | 4 |
| Logical 0 input current at output enable | IIN(0) | 0.005 | | 1 | µA | VCC=15V, VIN=0V | 4 |
| Logical 0 input voltage, CMOS/LPTTL interface (except Osc and KBM inputs) | VIN(0) | | | 0.8 | V | VCC=4.75V | 4 |
| Logical 1 output voltage, CMOS/LPTTL interface | VOUT(1) | 2.4 | | | V | IO=360µA, VCC=4.75V | 4 |
| Logical 0 output voltage, CMOS/LPTTL interface | VOUT(0) | | | 0.4 | V | IO=360µA, VCC=4.75V | 5 |
| Output source current, P-channel (VCC=5V) | ISOURCE | 1.75 | | 3.3 | mA | VCC=5V, VOUT=0V, TA=25°C | 5 |
| Output source current, P-channel (VCC=10V) | ISOURCE | 8 | | 15 | mA | VCC=10V, VOUT=0V, TA=25°C | 5 |
| Output sink current, N-channel (VCC=5V) | ISINK | 1.75 | | 3.6 | mA | VCC=5V, VOUT=VCC, TA=25°C | 5 |
| Output sink current, N-channel (VCC=10V) | ISINK | 8 | | 16 | mA | VCC=10V, VOUT=VCC, TA=25°C | 5 |
| Propagation delay to logical 0 or 1 from D.A. (VCC=5V) | tpd0, tpd1 | 60 | | 150 | ns | CL=50pF (Figure 1) | 5 |
| Propagation delay to logical 0 or 1 from D.A. (VCC=10V) | tpd0, tpd1 | 35 | | 80 | ns | CL=50pF (Figure 1) | 5 |
| Propagation delay to logical 0 or 1 from D.A. (VCC=15V) | tpd0, tpd1 | 25 | | 60 | ns | CL=50pF (Figure 1) | 5 |
| Propagation delay into high impedance state (VCC=5V) | t0H, t1H | 80 | | 200 | ns | RL=10k, CL=10pF (Figure 2), VCC=5V | 5 |
| Propagation delay into high impedance state (VCC=10V) | t0H, t1H | 65 | | 150 | ns | RL=10k, CL=10pF (Figure 2), VCC=10V | 5 |
| Propagation delay into high impedance state (VCC=15V) | t0H, t1H | 50 | | 110 | ns | RL=10k, CL=10pF (Figure 2), VCC=15V | 5 |
| Propagation delay from high impedance state (VCC=5V) | tH0, tH1 | 100 | | 250 | ns | RL=10k, CL=50pF (Figure 2), VCC=5V | 5 |
| Propagation delay from high impedance state (VCC=10V) | tH0, tH1 | 55 | | 125 | ns | RL=10k, CL=50pF (Figure 2), VCC=10V | 5 |
| Propagation delay from high impedance state (VCC=15V) | tH0, tH1 | 40 | | 90 | ns | RL=10k, CL=50pF (Figure 2), VCC=15V | 5 |
| Input capacitance | CIN | 5 | | 7.5 | pF | Any input (Note 4) | 5 |
| 3-STATE output capacitance | COUT | | | 10 | pF | Any output (Note 4) | 5 |
| Operating VCC range | VCC | 3 | | 15 | V | | 4 |
| Supply voltage, absolute maximum | VCC | | | 18 | V | | 4 |
| Operating temperature range | | -40 | | 85 | °C | XD/XL74C922, XD/XL74C923 | 4 |
| Storage temperature range | | -65 | | 150 | °C | | 4 |
| Power dissipation, small outline package | PD | | | 500 | mW | Small Outline | 4 |
| Lead temperature, soldering | | | | 260 | °C | 10 seconds soldering | 4 |
## CAD (KiCad official)
- Symbol: `XL74C922`
- Footprint: `Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm`
- 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files: `xl74c922-etched.step` / `xl74c922-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `xl74c922.step` / `xl74c922.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [XINLUDA datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589841370769883136) (11 pp, sha256 `5a5db127be601c00`, retrieved 2026-10-21, tier: lcsc)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/xl74c922-datasheet.pdf)