Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗

Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗

Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗

Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗

Loads when you scroll to it. Unloads after 5 minutes in the background.

Download PDF

Contents

Pinout
Key specifications
Electrical characteristics
CAD (KiCad official)
Provenance

README

markdown

XL7135CD

XINLUDA · Analog To Digital Converters (ADCs) · SOP-28-300mil

XL7135CD from XINLUDA, in a SOP-28-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VCC-	power_in	Negative supply, recommended -3 V to -8 V (nominal -5 V) with respect to ground, absolute maximum 15 V total between VCC+ and VCC-.
2	REF	input	Reference voltage input, positive with respect to analog common, recommended 1 V and within VCC- to VCC+.
3	ANLG COMMON	passive	Analog common, connected internally to IN- during auto-zero, deintegrate and zero-integrator phases; tie to the same point as IN- when IN- is at a fixed voltage.
4	INT OUT	output	Integrator output to which the integrating capacitor CINT connects (nominal 0.47 uF), keeping the swing at least 0.3 V from either supply.
5	AUTO ZERO	passive	Auto-zero capacitor CAZ connection (typical value 1 uF) used to compensate offsets of the buffer, integrator and comparator.
6	BUFF OUT	output	Buffer amplifier output that connects to the integrating resistor RINT, sized for an integrator current of nominally 20 uA.
7	Cref-	passive	Negative terminal of the external reference capacitor Cref (typical value 1 uF).
8	Cref+	passive	Positive terminal of the external reference capacitor Cref (typical value 1 uF).
9	IN-	input	Differential analog input low; voltage range VCC- to VCC+, can be tied to ANLG COMMON, input leakage typically 1 pA.
10	IN+	input	Differential analog input high; voltage range VCC- to VCC+, input leakage typically 1 pA.
11	VCC+	power_in	Positive supply, recommended 4 V to 6 V (nominal 5 V), supply current 1 mA typical at fclock = 0.
12	D5	output	Digit-drive output for the most significant digit, goes high for 200 clock pulses in sequence, VOH min 2.4 V at -1 mA.
13	B1	output	Multiplexed BCD output bit 1 (weight 1), VOH min 2.4 V at -1 mA.
14	B2	output	Multiplexed BCD output bit 2 (weight 2), VOH min 2.4 V at -1 mA.
15	B4	output	Multiplexed BCD output bit 4 (weight 4), VOH min 2.4 V at -1 mA.
16	B8	output	Multiplexed BCD output bit 8 (weight 8), VOH min 2.4 V at -1 mA.
17	D4	output	Digit-drive output for digit 4, goes high for 200 clock pulses in sequence, VOH min 2.4 V at -1 mA.
18	D3	output	Digit-drive output for digit 3, goes high for 200 clock pulses in sequence, VOH min 2.4 V at -1 mA.
19	D2	output	Digit-drive output for digit 2, goes high for 200 clock pulses in sequence, VOH min 2.4 V at -1 mA.
20	D1	output	Digit-drive output for the least significant digit, goes high for 200 clock pulses in sequence, VOH min 2.4 V at -1 mA.
21	BUSY	output	Goes high at the start of signal integrate and stays high until the first clock after zero crossing (or end of cycle on over-range).
22	CLK	input	Clock input, VIH min 2.8 V, VIL max 0.8 V, operating frequency up to 2 MHz max (120 kHz typical test condition).
23	POLARITY	output	Polarity output, high for a positive input signal, updated at the start of each deintegrate phase and valid for all inputs.
24	DGTL GND	power_in	Digital ground; return currents from digital circuits must not be sent to the analog ground line.
25	RUN/HOLD	input	High or open gives continuous conversions every 40,002 clock pulses; low holds the reading after the current cycle, and a positive pulse over 300 ns starts a new cycle (VIH min 2.8 V, VIL max 0.8 V).
26	STROBE	output	Active-low strobe pulse of 1/2 clock width at the midpoint of each digit drive, used to latch BCD data into external latches, UARTs or microprocessors.
27	OVER RANGE	output	Goes high after BUSY goes low at the end of a cycle when an over-range occurs, and goes low at the start of the next deintegrate phase.
28	UNDER RANGE	output	Goes high at the end of BUSY when the result is at or below 9% of full scale (count of 1800), low at the next signal integrate phase.

Key specifications

Parameter	Value
Manufacturer	XINLUDA
Package	SOP-28-300mil
Category	Data Converters
Pins	28

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage VCC+ to VCC-				15	V	over operating free-air temperature range	4
Storage temperature	Tstg	-65		150	°C		4
Operating free-air temperature (abs max)	TA	0		70	°C		4
Lead temperature				260	°C	1.6 mm (1/16 inch) from case for 10 seconds: N package	4
Supply voltage VCC+	VCC+	4	5	6	V		4
Supply voltage VCC-	VCC−	-3	-5	-8	V		4
Reference voltage	Vref		1		V		4
High-level input voltage, CLK, RUN/HOLD	VIH	2.8			V		4
Low-level input voltage, CLK, RUN/HOLD	VIL			0.8	V		4
Maximum operating frequency	fclock		1.2	2	MHz	see Note 1	4
Operating free-air temperature	TA	0		70	°C		4
High-level output voltage D1-D5,B1,B2,B4,B8	VOH	2.4	5		V	IO = −1 mA	4
High-level output voltage, other outputs	VOH	4.9	5		V	IO = −10 µA	4
Low-level output voltage	VOL			0.4	V	IO = 1.6 mA	4
Peak-to-peak output noise voltage	VON(PP)		15		µV	VID = 0, Full scale = 2 V	4
Zero-reading temperature coefficient of output voltage	VO		0.5	2	µV/°C	VID = 0, 0°C ≤ TA ≤ 70°C	4
High-level input current	IIH		0.1	10	µA	VI = 5 V, 0°C ≤ TA ≤ 70°C	4
Low-level input current	IIL		-0.02	-0.1	mA	VI = 0 V, 0°C ≤ TA ≤ 70°C	4
Input leakage current, IN− and IN+	II		1	10	pA	VID = 0, TA = 25°C	4
Input leakage current, IN− and IN+	II			250	pA	VID = 0, 0°C ≤ TA ≤ 70°C	4
Positive supply current	ICC+		1	2	mA	fclock = 0, TA = 25°C	4
Positive supply current	ICC+			3	mA	fclock = 0, 0°C ≤ TA ≤ 70°C	4
Negative supply current	ICC−		-0.8	-2	mA	fclock = 0, TA = 25°C	4
Negative supply current	ICC−			-3	mA	fclock = 0, 0°C ≤ TA ≤ 70°C	4
Power dissipation capacitance	Cpd		40		pF	See Note 2	4
Full-scale temperature coefficient	FS			5	ppm/°C	VID = 2 V, 0°C ≤ TA ≤ 70°C	5
Linearity error	EL		0.5		count	−2 V ≤ VID ≤ 2 V	5
Differential linearity error	ED		0.01		LSB	−2 V ≤ VID ≤ 2 V	5
Full-scale symmetry error (rollover error)	EFS		0.5	1	count	VID = 2 V	5
Display reading with 0-V input		0	0	0	Digital Reading	VID = 0, 0°C ≤ TA ≤ 70°C	5
Display reading in ratiometric operation		0.9998	0.9999	1	Digital Reading	VID = Vref, TA = 25°C	5
Display reading in ratiometric operation		0.9995	0.9999	1.0005	Digital Reading	0°C ≤ TA ≤ 70°C	5

CAD (KiCad official)

Symbol: XL7135CD
Footprint: Package_SO:SOP-28_8.4x18.16mm_P1.27mm
3D model: SOP-28-300mil (KiCad packages3D, STEP)
3D model files: xl7135cd-etched.step / xl7135cd-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xl7135cd.step / xl7135cd.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: XINLUDA datasheet (12 pp, sha256 2d6fffa5a1025a21, retrieved 2026-10-22, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF