component
XL551
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XINLUDA Timers / Clock Oscillators, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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XL551
XINLUDA · Timers / Clock Oscillators · SOP-8
XL551 from XINLUDA, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground reference. All voltage values are with respect to network GND. |
| 2 | TRIG | input | Trigger input. Start of timing input. When TRIG < 1/2 CONT (approximately 1/3 VDD by default), the internal flip-flop is set, driving OUT high and turning off the discharge switch. |
| 3 | OUT | output | High-current timer output signal. VOH typ 4.8V at IOH=1mA (VDD=5V); VOL typ 0.21V at IOL=8mA. Sinks up to 100mA and sources up to 10mA typical. |
| 4 | RESET | input | Active-low reset input. When held low, forces OUT low and turns the discharge switch on, overriding all other inputs. Tie high (to VDD) when unused to prevent false triggering. |
| 5 | CONT | input | Control voltage input. Sets comparator thresholds; nominally at 2/3 VDD (open-circuit typ 66.7% of VDD). Allows bypass capacitor connection (typically 10nF to GND) or external threshold override. |
| 6 | THRES | input | Threshold input. End of timing input. When THRES > CONT (approximately 2/3 VDD by default), the internal flip-flop is reset, driving OUT low and turning the discharge switch on. |
| 7 | DISCH | output | Discharge. Open-collector output used to discharge the external timing capacitor to GND when OUT is low. Provides a low-impedance path to GND during the reset/low-output state. |
| 8 | VDD | power_in | Power-supply voltage. Recommended operating range 2V to 15V; absolute maximum 17.5V. Typical IDD = 170uA at VDD=5V (max 350uA at 25 degC). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | SOP-8 |
| Category | RTC |
| Pins | 8 |
Ordering variants
Same part, different packaging or reel option.
XL551XL551XD551
CAD (KiCad official)
- Symbol:
XL551 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
xl551-etched.step/xl551-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);xl551.step/xl551.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XINLUDA datasheet (12 pp, sha256
8c2a047422caeea7, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# XL551
**XINLUDA** · Timers / Clock Oscillators · SOP-8
XL551 from XINLUDA, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground reference. All voltage values are with respect to network GND. |
| 2 | TRIG | input | Trigger input. Start of timing input. When TRIG < 1/2 CONT (approximately 1/3 VDD by default), the internal flip-flop is set, driving OUT high and turning off the discharge switch. |
| 3 | OUT | output | High-current timer output signal. VOH typ 4.8V at IOH=1mA (VDD=5V); VOL typ 0.21V at IOL=8mA. Sinks up to 100mA and sources up to 10mA typical. |
| 4 | RESET | input | Active-low reset input. When held low, forces OUT low and turns the discharge switch on, overriding all other inputs. Tie high (to VDD) when unused to prevent false triggering. |
| 5 | CONT | input | Control voltage input. Sets comparator thresholds; nominally at 2/3 VDD (open-circuit typ 66.7% of VDD). Allows bypass capacitor connection (typically 10nF to GND) or external threshold override. |
| 6 | THRES | input | Threshold input. End of timing input. When THRES > CONT (approximately 2/3 VDD by default), the internal flip-flop is reset, driving OUT low and turning the discharge switch on. |
| 7 | DISCH | output | Discharge. Open-collector output used to discharge the external timing capacitor to GND when OUT is low. Provides a low-impedance path to GND during the reset/low-output state. |
| 8 | VDD | power_in | Power-supply voltage. Recommended operating range 2V to 15V; absolute maximum 17.5V. Typical IDD = 170uA at VDD=5V (max 350uA at 25 degC). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | SOP-8 |
| Category | RTC |
| Pins | 8 |
## Ordering variants
Same part, different packaging or reel option.
- `XL551`
- `XL551XD551`
## CAD (KiCad official)
- Symbol: `XL551`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `xl551-etched.step` / `xl551-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `xl551.step` / `xl551.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [XINLUDA datasheet](docs/xl551-datasheet.pdf) (12 pp, sha256 `8c2a047422caeea7`, retrieved 2026-08-17, tier: lcsc)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/xl551-datasheet.pdf)