component

XL4301E1

Public Made by Adom

by adom

XLSEMI DC-DC Converters, SOIC-8-EP. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs xl4301e1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
package.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
pads.json add symbol pin "9" for the exposed thermal pad: the footprint carries the pad and the symbol had none, so it reached no net (vendor string 'SOIC-8-EP' denotes an exposed pad) · Ray 1mo ago
page.json xl4301e1: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 20h ago
README.md xl4301e1: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 16d ago
xl4301e1-etched.fit.json xl4301e1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
xl4301e1-etched.glb xl4301e1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
xl4301e1-etched.step xl4301e1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
xl4301e1.glb fix footprint: SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm -> SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm (3d refresh; body regenerated from the footprint F.Fab outline) · Ray 1mo ago
xl4301e1.kicad_mod fix footprint: SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm -> SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm (ep_dropped, 8 pins; datasheet EP 3.302x2.413mm, land 2.41x3.3mm (Δ0.005mm)) · Ray 1mo ago
xl4301e1.kicad_sym add symbol pin "9" for the exposed thermal pad: the footprint carries the pad and the symbol had none, so it reached no net (vendor string 'SOIC-8-EP' denotes an exposed pad) · Ray 1mo ago
xl4301e1.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect and oval pad as a SQUARE EAGLE smd; this carries the real pad shape across (0 -> 8 rounded pads) and stops dropping geometry drawn on KiCad User.N layers. Attributes, connects, pads and the pin-1 marker are gated against decreasing and are unchanged. · Ray 1mo ago
xl4301e1.step fix footprint: SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm -> SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm (3d refresh; body regenerated from the footprint F.Fab outline) · Ray 1mo ago

XL4301E1

XLSEMI · DC-DC Converters · SOIC-8-EP

XL4301E1 from XLSEMI, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected Not connected. Leave floating or tie to ground per PCB convention.
2 SW output Power switch output. Drain of the internal high-side MOSFET; connects to the external inductor/catch diode of the buck converter. The back exposed pad is internally tied to SW and should be connected to this node on the PCB.
3 GND power_in Ground reference for the IC and the return for the input/output bypass capacitors.
4 FB input Feedback input to the internal error amplifier. Senses the regulated output through an external resistor divider; regulation threshold is 1.25 V typical (VOUT = 1.25 V x (1 + R2/R1)).
5 CS input Output current sense input for the constant-current loop. Load current is set by an external sense resistor: Iload = 0.11 V / RCS (VCS typ. 110 mV).
6 LC input Output cable-loss compensation input. A user-programmable resistor (R3) from this pin to ground selects the amount of voltage-drop compensation added to the output as a function of load current (see Table 2).
7 VC passive Internal voltage regulator bypass pin. Connect a 1 uF capacitor from VC to VIN to decouple the internal LDO that supplies the control circuitry.
8 VIN power_in Supply voltage input, 8 V to 40 V DC operating range (45 V absolute maximum). Bypass to GND with a suitably large low-ESR capacitor (e.g. 100 uF/50 V) close to the pin to eliminate input noise.

Key specifications

Parameter Value
Manufacturer XLSEMI
Package SOIC-8-EP
Category PMIC
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • XL4301E1

CAD (KiCad official)

  • Symbol: XL4301E1
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm
  • 3D model: SOIC-8-EP (KiCad packages3D, STEP)
  • 3D model files: xl4301e1-etched.step / xl4301e1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xl4301e1.step / xl4301e1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XLSEMI datasheet (10 pp, sha256 3f3b4c16d0fca911, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF