component
XL4021B
Public Made by Adomby adom
XINLUDA Shift Registers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"number": "1",
"name": "PI-8",
"type": "input",
"description": "Parallel data input for register stage 8, loaded when PARALLEL/SERIAL CONTROL is high; input voltage must stay within VSS-0.5 V to VDD+0.5 V and input current is limited to ±10 mA."
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{
"number": "2",
"name": "Q6",
"type": "output",
"description": "Buffered output taken from register stage 6 of the 8-stage shift register."
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{
"number": "3",
"name": "Q8",
"type": "output",
"description": "Buffered output of register stage 8, the final stage of the shift register."
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{
"number": "4",
"name": "PI-4",
"type": "input",
"description": "Parallel data input for register stage 4, loaded when PARALLEL/SERIAL CONTROL is high; input voltage must stay within VSS-0.5 V to VDD+0.5 V and input current is limited to ±10 mA."
},
{
"number": "5",
"name": "PI-3",
"type": "input",
"description": "Parallel data input for register stage 3, loaded when PARALLEL/SERIAL CONTROL is high; input voltage must stay within VSS-0.5 V to VDD+0.5 V and input current is limited to ±10 mA."
},
{
"number": "6",
"name": "PI-1",
"type": "input",
"description": "Parallel data input for register stage 1, loaded when PARALLEL/SERIAL CONTROL is high; input voltage must stay within VSS-0.5 V to VDD+0.5 V and input current is limited to ±10 mA."
},
{
"number": "7",
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"description": "Parallel data input for register stage 2, loaded when PARALLEL/SERIAL CONTROL is high; input voltage must stay within VSS-0.5 V to VDD+0.5 V and input current is limited to ±10 mA."
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{
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"description": "Selects entry mode: low shifts serial data in on the positive clock edge, high jams the parallel inputs into the register."
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{
"number": "10",
"name": "CLOCK",
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"description": "Clock input; serial and parallel entry are synchronized to its positive transition, with recommended clock frequency up to 3 MHz at 5 V, 6 MHz at 10 V and 8.5 MHz at 15 V."
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{
"number": "11",
"name": "SERIAL IN",
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"description": "Serial data input, shifted into the register synchronously with the positive clock transition when PARALLEL/SERIAL CONTROL is low."
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{
"number": "12",
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"description": "Buffered output taken from register stage 7 of the 8-stage shift register."
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{
"number": "13",
"name": "PI-5",
"type": "input",
"description": "Parallel data input for register stage 5, loaded when PARALLEL/SERIAL CONTROL is high; input voltage must stay within VSS-0.5 V to VDD+0.5 V and input current is limited to ±10 mA."
},
{
"number": "14",
"name": "PI-6",
"type": "input",
"description": "Parallel data input for register stage 6, loaded when PARALLEL/SERIAL CONTROL is high; input voltage must stay within VSS-0.5 V to VDD+0.5 V and input current is limited to ±10 mA."
},
{
"number": "15",
"name": "PI-7",
"type": "input",
"description": "Parallel data input for register stage 7, loaded when PARALLEL/SERIAL CONTROL is high; input voltage must stay within VSS-0.5 V to VDD+0.5 V and input current is limited to ±10 mA."
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{
"number": "16",
"name": "VDD",
"type": "power_in",
"description": "Positive supply voltage, recommended 3 V to 18 V with an absolute maximum of +20 V referenced to VSS."
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],
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"name": "Quiescent device current",
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"conditions": "VIN=0 V, VDD=5 V, TA=+25°C",
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"name": "Quiescent device current",
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{
"name": "Output low (sink) current",
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