component
XL4021B
Public Made by Adomby adom
XINLUDA Shift Registers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
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"version": "0.1.0",
"type": "component",
"description": "XINLUDA Shift Registers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
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"logic",
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"factory-2.0.0",
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"component": {
"mpn": "XL4021B",
"manufacturer": "XINLUDA",
"package": "SOP-16",
"pin_count": 16,
"category": "Logic",
"subcategory": "Shift Registers",
"datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8758160387458387968",
"parts": {
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"distributor_links": {
"lcsc": "C17179541"
},
"distributor_check": {
"checked_at": "2026-10-18T03:01:30Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": null,
"status": "no match"
},
"mouser": {
"pn": null,
"status": "no match"
}
},
"pins": [
{
"number": "1",
"name": "PI-8",
"type": "input",
"description": "Parallel data input for register stage 8, loaded when PARALLEL/SERIAL CONTROL is high; input voltage must stay within VSS-0.5 V to VDD+0.5 V and input current is limited to ±10 mA."
},
{
"number": "2",
"name": "Q6",
"type": "output",
"description": "Buffered output taken from register stage 6 of the 8-stage shift register."
},
{
"number": "3",
"name": "Q8",
"type": "output",
"description": "Buffered output of register stage 8, the final stage of the shift register."
},
{
"number": "4",
"name": "PI-4",
"type": "input",
"description": "Parallel data input for register stage 4, loaded when PARALLEL/SERIAL CONTROL is high; input voltage must stay within VSS-0.5 V to VDD+0.5 V and input current is limited to ±10 mA."
},
{
"number": "5",
"name": "PI-3",
"type": "input",
"description": "Parallel data input for register stage 3, loaded when PARALLEL/SERIAL CONTROL is high; input voltage must stay within VSS-0.5 V to VDD+0.5 V and input current is limited to ±10 mA."
},
{
"number": "6",
"name": "PI-1",
"type": "input",
"description": "Parallel data input for register stage 1, loaded when PARALLEL/SERIAL CONTROL is high; input voltage must stay within VSS-0.5 V to VDD+0.5 V and input current is limited to ±10 mA."
},
{
"number": "7",
"name": "PI-2",
"type": "input",
"description": "Parallel data input for register stage 2, loaded when PARALLEL/SERIAL CONTROL is high; input voltage must stay within VSS-0.5 V to VDD+0.5 V and input current is limited to ±10 mA."
},
{
"number": "8",
"name": "VSS",
"type": "power_in",
"description": "Negative supply voltage; all voltages in the datasheet are referenced to this terminal."
},
{
"number": "9",
"name": "PARALLEL/SERIAL CONTROL",
"type": "input",
"description": "Selects entry mode: low shifts serial data in on the positive clock edge, high jams the parallel inputs into the register."
},
{
"number": "10",
"name": "CLOCK",
"type": "input",
"description": "Clock input; serial and parallel entry are synchronized to its positive transition, with recommended clock frequency up to 3 MHz at 5 V, 6 MHz at 10 V and 8.5 MHz at 15 V."
},
{
"number": "11",
"name": "SERIAL IN",
"type": "input",
"description": "Serial data input, shifted into the register synchronously with the positive clock transition when PARALLEL/SERIAL CONTROL is low."
},
{
"number": "12",
"name": "Q7",
"type": "output",
"description": "Buffered output taken from register stage 7 of the 8-stage shift register."
},
{
"number": "13",
"name": "PI-5",
"type": "input",
"description": "Parallel data input for register stage 5, loaded when PARALLEL/SERIAL CONTROL is high; input voltage must stay within VSS-0.5 V to VDD+0.5 V and input current is limited to ±10 mA."
},
{
"number": "14",
"name": "PI-6",
"type": "input",
"description": "Parallel data input for register stage 6, loaded when PARALLEL/SERIAL CONTROL is high; input voltage must stay within VSS-0.5 V to VDD+0.5 V and input current is limited to ±10 mA."
},
{
"number": "15",
"name": "PI-7",
"type": "input",
"description": "Parallel data input for register stage 7, loaded when PARALLEL/SERIAL CONTROL is high; input voltage must stay within VSS-0.5 V to VDD+0.5 V and input current is limited to ±10 mA."
},
{
"number": "16",
"name": "VDD",
"type": "power_in",
"description": "Positive supply voltage, recommended 3 V to 18 V with an absolute maximum of +20 V referenced to VSS."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The pin-function table lists 'Q6, Q7, Q8' against pins '2, 3, 12' in that order, which would make pi; Parallel-input pin-to-stage mapping was taken by matching the ordered pin list (6,7,5,4,13,14,15,1 =; The datasheet is internally inconsistent on parallel-entry timing: Section 1 says parallel entry is "
],
"pages_sent": 10,
"cost_usd": 0.0569,
"at": "2026-10-18T02:58:45"
},
"datasheet": {
"url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8758160387458387968",
"pages": 10,
"sha256": "1c36cab23d66cacb",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 16,
"described": 16,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
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}