component
XL33290
Public Made by Adomby adom
XINLUDA Interface - Specialized, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 4d ago |
| viewers | 4d ago |
| package.json | 4d ago |
| page.json | 4d ago |
| README.md | 4d ago |
| verification.json | 4d ago |
| xl33290-etched.glb | 4d ago |
| xl33290-etched.step | 4d ago |
| xl33290-hero.glb | 4d ago |
| xl33290-hero.overlay.json | 4d ago |
| xl33290.glb | 4d ago |
| xl33290.kicad_mod | 4d ago |
| xl33290.kicad_sym | 4d ago |
| xl33290.lbr | 4d ago |
| xl33290.step | 4d ago |
XL33290
XINLUDA · Interface - Specialized · SOP-8
XL33290 from XINLUDA, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBB | power_in | Battery power input supplied through an external resistor and diode, specified for 8.0 V to 18 V. |
| 2 | NC | unconnected | Not to be connected, and NC pins are not guaranteed to be open circuits. |
| 3 | GND | power_in | Common signal and power return. |
| 4 | ISO | bidirectional | ISO K line bus connection, protected against shorts to ground and overtemperature. |
| 5 | TX | input | Logic level input for data to be transmitted on the bus, with an internal pull-up to VDD. |
| 6 | RX | output | Logic output of data received from the bus. |
| 7 | VDD | power_in | Logic power supply input, specified for 4.75 V to 5.25 V. |
| 8 | CEN | input | Chip enable, where logic 1 is the active state and logic 0 is the sleep state, with an internal pull-down. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | SOP-8 |
| Category | Interface ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD Sleep State Current | IDD(SS) | 0.1 | mA | Tx = 0.8 VDD, CEN = 0.3 VDD | 5 | ||
| VDD Quiescent Operating Current | IDD(Q) | 1 | mA | Tx = 0.2 VDD, CEN = 0.7 VDD | 5 | ||
| VBB Sleep State Current | IBB(SS) | 50 | µA | VBB = 16 V, Tx = 0.8 VDD, CEN = 0.3 VDD | 5 | ||
| VBB Quiescent Operating Current | IBB(Q) | 1 | mA | TX = 0.2 VDD, CEN = 0.7 VDD | 5 | ||
| Chip Enable Input High-Voltage Threshold | VIH(CEN) | 0.7 | V | 5 | |||
| Chip Enable Input Low-Voltage Threshold | VIL(CEN) | 0.3 | V | 5 | |||
| Chip Enable Pull-Down Current | IPD(CEN) | 2 | 40 | µA | 5 | ||
| TX Input Low-Voltage Threshold | VIL(Tx) | 0.3 | V | RISO = 510 Ω | 5 | ||
| TX Input High-Voltage Threshold | VIH(Tx) | 0.7 | V | RISO = 510 Ω | 5 | ||
| TX Pull-Up Current | IPU(Tx) | -40 | -2 | µA | 5 | ||
| RX Output Low-Voltage Threshold | VOL(Rx) | 0.2 | V | RISO = 510 Ω, TX = 0.2 VDD, Rx Sinking 1.0 mA | 5 | ||
| RX Output High-Voltage Threshold | VOH(Rx) | 0.8 | V | RISO = 510 Ω, TX = 0.8 VDD, RX Sourcing 250 µA | 5 | ||
| Thermal Shutdown | TLIM | 150 | 170 | °C | 5 | ||
| ISO Input Low Voltage Threshold | VIL(ISO) | 0.4 | V | RISO = 0 , TX = 0.8 VDD | 6 | ||
| ISO Input High Voltage Threshold | VIH(ISO) | 0.7 | V | RISO = 0 , TX = 0.8 VDD | 6 | ||
| ISO Input Hysteresis | VHys(ISO) | 0.05 | 0.1 | V | 6 | ||
| ISO Internal Pull-Up Current | IPU(ISO) | -5 | -140 | µA | RISO = [symbol not extracted], TX = 0.8 VDD, VISO = 9.0 V, VBB = 18 V | 6 | |
| ISO Short Circuit Current Limit | ISC(ISO) | 50 | 100 | mA | RISO = 0 , TX = 0.4 VDD, VISO = VBB | 6 | |
| ISO Output Low Voltage | VOL(IS) | 0.1 | V | RISO = 510 Ω, TX = 0.2 VDD | 6 | ||
| ISO Output High Voltage | VOH(IS) | 0.95 | V | RISO = [symbol not extracted], TX = 0.8 VDD | 6 | ||
| ISO Fall Time | tfall(ISO) | 2 | µs | RISO = 510 Ω to VBB, CISO = 10 nF to Ground | 6 | ||
| ISO Propagation Delay High to Low | tPD(ISO) | 2 | µs | High to Low: RISO = 510 Ω, CISO = 500 pF | 6 | ||
| ISO Propagation Delay Low to High | tPD(ISO) | 2 | µs | Low to High: RISO = 510 Ω, CISO = 500 pF | 6 | ||
| DC Supply Voltage | VDD | -0.3 | 7 | V | 4 | ||
| Load Dump Peak Voltage | VBB(LD) | 45 | V | 4 | |||
| ISO Pin Load Dump Peak Voltage | VISO | 40 | V | 4 | |||
| ISO Short Circuit Current Limit | ISO(LIM) | 1 | A | 4 | |||
| ESD Voltage Human Body Model | VESD1 | -2000 | 2000 | V | Human Body Model | 4 | |
| ESD Voltage Machine Model | VESD2 | -200 | 200 | V | Machine Model | 4 | |
| ISO Clamp Energy | Eclamp | 10 | mJ | 4 | |||
| Storage Temperature | Tstg | -55 | 150 | °C | 4 | ||
| Operating Case Temperature | TC | -40 | 85 | °C | 4 | ||
| Operating Junction Temperature | TJ | -45 | 125 | °C | 4 | ||
| Power Dissipation | PD | 0.8 | W | TA = 25°C | 4 | ||
| Supply Voltage VDD (parametric range) | VDD | 4.75 | 5.25 | V | Characteristics noted under conditions of, unless otherwise noted | 5 | |
| Battery Voltage VBB (parametric range) | VBB | 8 | 18 | V | Characteristics noted under conditions of, unless otherwise noted | 5 | |
| Case Temperature (parametric range) | TC | -40 | 85 | °C | Characteristics noted under conditions of, unless otherwise noted | 5 | |
| Thermal Resistance Junction-to-Ambient | RJA | 150 | °C/W | 4 |
CAD (KiCad official)
- Symbol:
XL33290 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
xl33290-etched.step/xl33290-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);xl33290.step/xl33290.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XINLUDA datasheet (8 pp, sha256
ee31deea260aa6d8, retrieved 2026-11-05, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).