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XL2543

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XINLUDA Analog To Digital Converters (ADCs), SOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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XL2543

XINLUDA · Analog To Digital Converters (ADCs) · SOP-20

XL2543 from XINLUDA, in a SOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AIN0 input Analog input 0, one of 11 multiplexed analog inputs; source impedance should be ≤50 Ω for 4.1-MHz I/O CLOCK operation.
2 AIN1 input Analog input 1, one of 11 multiplexed analog inputs; source impedance should be ≤50 Ω for 4.1-MHz I/O CLOCK operation.
3 AIN2 input Analog input 2, one of 11 multiplexed analog inputs; source impedance should be ≤50 Ω for 4.1-MHz I/O CLOCK operation.
4 AIN3 input Analog input 3, one of 11 multiplexed analog inputs; source impedance should be ≤50 Ω for 4.1-MHz I/O CLOCK operation.
5 AIN4 input Analog input 4, one of 11 multiplexed analog inputs; source impedance should be ≤50 Ω for 4.1-MHz I/O CLOCK operation.
6 AIN5 input Analog input 5, one of 11 multiplexed analog inputs; source impedance should be ≤50 Ω for 4.1-MHz I/O CLOCK operation.
7 AIN6 input Analog input 6, one of 11 multiplexed analog inputs; source impedance should be ≤50 Ω for 4.1-MHz I/O CLOCK operation.
8 AIN7 input Analog input 7, one of 11 multiplexed analog inputs; source impedance should be ≤50 Ω for 4.1-MHz I/O CLOCK operation.
9 AIN8 input Analog input 8, one of 11 multiplexed analog inputs; source impedance should be ≤50 Ω for 4.1-MHz I/O CLOCK operation.
10 GND power_in Ground return terminal for the internal circuitry; all voltage measurements are with respect to GND.
11 AIN9 input Analog input 9, one of 11 multiplexed analog inputs; source impedance should be ≤50 Ω for 4.1-MHz I/O CLOCK operation.
12 AIN10 input Analog input 10, one of 11 multiplexed analog inputs; source impedance should be ≤50 Ω for 4.1-MHz I/O CLOCK operation.
13 REF- input Negative reference voltage, nominally ground, that sets the lower end of the input range.
14 REF+ input Positive reference voltage, nominally VCC; the input range is set by the difference between REF+ and REF-.
15 CS input Chip select; a high-to-low transition resets the internal counters and enables DATA OUT, DATA INPUT and I/O CLOCK, and a low-to-high transition disables DATA INPUT and I/O CLOCK.
16 DATA OUT tri_state 3-state serial output for the A/D conversion result; high-impedance when CS is high and active when CS is low, with data changing on the falling edge of I/O CLOCK.
17 DATA INPUT input Serial-data input; a 4-bit address, MSB first, selects the analog input or test voltage to convert next and is shifted in on the first four rising edges of I/O CLOCK.
18 I/O CLOCK input Input/output clock that clocks in the input data bits, shifts out the previous conversion data on DATA OUT, and hands control to the internal state controller on the last falling edge; max 4.1 MHz.
19 EOC output End of conversion; goes low after the falling edge of the last I/O CLOCK and stays low until the conversion is complete and data is ready for transfer.
20 VCC power_in Positive supply voltage, 4.5 V to 5.5 V recommended (5 V nominal).

Key specifications

Parameter Value
Manufacturer XINLUDA
Package SOP-20
Category ADC/DAC/Data Conversion
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High-level output voltage VOH 2.4 V VCC = 4.5 V, IOH = -1.6 mA 5
Low-level output voltage VOL 0.4 V VCC = 4.5 V, IOL = 1.6 mA 5
Low-level output voltage VOL 0.1 V VCC = 4.5 V to 5.5 V, IOL = 20 µA 5
High-impedance off-state output current IOZ 1 2.5 µA VO = VCC, CS at VCC 5
High-impedance off-state output current IOZ -2.5 1 µA VO = 0, CS at VCC 5
High-level input current IIH 1 10 µA VI = VCC 5
Low-level input current IIL -10 1 µA VI = 0 5
Operating supply current ICC 1 2.5 mA CS at 0 V 5
Power-down current ICC(PD) 4 25 µA For all digital inputs, 0 ≤ VI ≤ 0.5 V or VI ≥ VCC, 0.5 V 5
Selected channel leakage current 10 µA Selected channel at VCC, Unselected channel at 0 V 5
Selected channel leakage current -10 µA Selected channel at 0 V, Unselected channel at VCC 5
Maximum static analog reference current into REF+ 1 2.5 µA Vref+ = VCC, Vref- = GND 5
Input capacitance, analog inputs Ci 30 60 pF Analog inputs 5
Input capacitance, control inputs Ci 5 15 pF Control inputs 5
Linearity error EL 1 LSB See Figure 2 6
Differential linearity error ED 1 LSB See Figure 2 6
Offset error EO 1.5 LSB See Note 2 and Figure 2 6
Gain error EG 1 LSB See Note 2 and Figure 2 6
Total unadjusted error ET 1.75 LSB 6
Conversion time t(conv) 8 10 µs See Figures 9-14 6
Valid time, DATA OUT remains valid after I/O CLOCK tv 10 ns See Figure 6 6
Delay time, I/O CLOCK to DATA OUT valid td(I/O-DATA) 150 ns See Figure 6 6
Delay time, last I/O CLOCK to EOC td(I/O-EOC) 1.5 2.2 µs See Figure 7 6
Delay time, EOC to DATA OUT (MSB/LSB) td(EOC-DATA) 100 ns See Figure 8 6
Enable time, CS to DATA OUT tPZH, tPZL 0.7 1.3 µs See Figure 3 6
Disable time, CS to DATA OUT tPHZ, tPLZ 70 150 ns See Figure 3 6
Rise time, EOC tr(EOC) 15 50 ns See Figure 8 6
Fall time, EOC tf(EOC) 15 50 ns See Figure 7 6
Rise time, data bus tr(bus) 15 50 ns See Figure 6 6
Fall time, data bus tf(bus) 15 50 ns See Figure 6 6
Supply voltage VCC 4.5 5 5.5 V 4
Differential reference voltage Vref+, Vref- 2.5 V see Note 2 4
Analog input voltage 0 V see Note 2 4
High-level control input voltage VIH 2 V VCC = 4.5 V to 5.5 V 4
Low-level control input voltage VIL 0.8 V VCC = 4.5 V to 5.5 V 4
Clock frequency at I/O CLOCK 0 4.1 MHz 4
Setup time, address bits at DATA INPUT before I/O CLOCK tsu(A) 100 ns see Figure 4 4
Hold time, address bits after I/O CLOCK th(A) 0 ns see Figure 4 4
Hold time, CS low after last I/O CLOCK th(CS) 0 ns see Figure 5 4
Setup time, CS low before clocking in first address bit tsu(CS) 1.425 µs see Note 3 and Figure 5 4
Pulse duration, I/O CLOCK high twH(I/O) 120 ns 4
Pulse duration, I/O CLOCK low twL(I/O) 120 ns 4
Transition time, I/O CLOCK high to low tt(I/O) 1 µs see Note 4 and Figure 6 4
Transition time, DATA INPUT and CS tt(CS) 10 µs 4
Operating free-air temperature TA -40 85 °C 4
Supply voltage range VCC 6.5 V 4
Input voltage range VIN -0.3 V upper limit VCC + 0.3 V 4
Peak input current (any input) II -20 20 mA 4
Peak total input current (all inputs) II 30 mA 4
Operating free-air temperature range TA -40 85 °C 4
Storage temperature range Tstg -65 150 °C 4
Lead temperature Tl 260 °C 1,6 mm (1/16 inch) from the case for 10 seconds 4

CAD (KiCad official)

  • Symbol: XL2543
  • Footprint: Package_SO:SOP-20_7.5x12.8mm_P1.27mm
  • 3D model: SOP-20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: xl2543-etched.step / xl2543-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xl2543.step / xl2543.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (23 pp, sha256 e2b9780c35509c29, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF