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XL0832DR
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XINLUDA Analog To Digital Converters (ADC), SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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XL0832DR
XINLUDA · Analog To Digital Converters (ADC) · SOP-8
XL0832DR from XINLUDA, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Chip select, active low: it must be held low for the entire conversion, and taking it high ends the process and disables the chip. |
| 2 | CH0 | passive | Analog input channel 0, configurable as IN+ or IN- in differential mode or as a single-ended input. |
| 3 | CH1 | passive | Analog input channel 1, configurable as IN+ or IN- in differential mode or as a single-ended input. |
| 4 | GND | power_in | Ground reference for the device. |
| 5 | DI | input | Serial data input that carries the start bit and the channel/polarity configuration bits, latched on each CLK rising edge; it is ignored after the third clock pulse of addressing. |
| 6 | DO | tri_state | Serial conversion data output, MSB first on the first byte and then LSB first on the second; it is high-impedance while CS is high and not in the output phase, and the CLK-falling-to-valid-data delay is 2000 ns maximum (MSB first, 100 pF load). |
| 7 | CLK | input | Serial clock input with a working frequency of 10 kHz to 400 kHz and a 40% to 60% duty cycle. |
| 8 | VCC/REF | power_in | Supply input (4.5 V minimum, 5.0 V nominal per the electrical table; absolute maximum VCC is 6.5 V) that also serves as the reference voltage input. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | SOP-8 |
| Category | Data Acquisition |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply current | ICC | 2 | mA | 3 | |||
| Power supply | VCC | 4.5 | V | 3 | |||
| Logical 1 input voltage (min) | VIH | 2 | V | VCC=5.25V | 3 | ||
| Logical 0 input voltage (max) | VIL | 0.8 | V | VCC=4.75V | 3 | ||
| Logical 1 input current (max) | IIH | 10 | µA | VIN=5.0V | 3 | ||
| Logical 0 input current (max) | IIL | -10 | µA | VIN=0V | 3 | ||
| Logical 1 output voltage (min) | VOH | 2.4 | V | VCC=4.75V, IOUT=−360 µA | 3 | ||
| Logical 1 output voltage (min) | VOH | 4.5 | V | VCC=4.75V, IOUT=−10 µA | 3 | ||
| Logical 0 output voltage (max) | VOL | 0.4 | V | VCC=4.75V, IOUT=1.6mA | 3 | ||
| Output source current (min) | ISOURCE | -6.5 | -14 | mA | VOUT=0V | 3 | |
| Output sink current (min) | ISINK | 8 | 16 | mA | VOUT=VCC | 3 | |
| Working clock frequency | fCLK | 10 | 400 | kHz | 3 | ||
| Conversion time | tC | 8 | 1/fCLK | Not including MUX addressing time | 3 | ||
| Clock duty cycle | 40 | 60 | % | 3 | |||
| Data input valid after CLK rising edge (hold) | tHOLD | 200 | ns | 3 | |||
| CLK falling edge to output data valid, MSB first | tpd1 | 2000 | ns | CL=100 pF, data MSB first | 3 | ||
| CLK falling edge to output data valid, LSB first | tpd0 | 1000 | ns | CL=100 pF, data LSB first | 3 | ||
| Rising edge of CS to data output and SAR Hi-Z | t1H,t0H | 400 | ns | CL=10 pF, RL=10k | 3 | ||
| VCC end to GND voltage | VCC | -0.5 | 6.5 | V | VCC end to GND | 2 | |
| Storage temperature | -65 | 150 | °C | 2 | |||
| Operating ambient temperature | -20 | 85 | °C | 2 | |||
| Welding temperature | 260 | °C | 10 seconds | 2 | |||
| Maximum junction temperature | 150 | °C | 2 | ||||
| Diffusion power dissipation | 0.8 | W | 2 | ||||
| ESD (HBM) withstand voltage | 4 | KV | HBM | 2 | |||
| Operating temperature range (ordering table) | -20 | 85 | °C | 6 |
CAD (KiCad official)
- Symbol:
XL0832DR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
xl0832dr-etched.step/xl0832dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);xl0832dr.step/xl0832dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XINLUDA datasheet (7 pp, sha256
87c7ef837612e9ba, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# XL0832DR
**XINLUDA** · Analog To Digital Converters (ADC) · SOP-8
XL0832DR from XINLUDA, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Chip select, active low: it must be held low for the entire conversion, and taking it high ends the process and disables the chip. |
| 2 | CH0 | passive | Analog input channel 0, configurable as IN+ or IN- in differential mode or as a single-ended input. |
| 3 | CH1 | passive | Analog input channel 1, configurable as IN+ or IN- in differential mode or as a single-ended input. |
| 4 | GND | power_in | Ground reference for the device. |
| 5 | DI | input | Serial data input that carries the start bit and the channel/polarity configuration bits, latched on each CLK rising edge; it is ignored after the third clock pulse of addressing. |
| 6 | DO | tri_state | Serial conversion data output, MSB first on the first byte and then LSB first on the second; it is high-impedance while CS is high and not in the output phase, and the CLK-falling-to-valid-data delay is 2000 ns maximum (MSB first, 100 pF load). |
| 7 | CLK | input | Serial clock input with a working frequency of 10 kHz to 400 kHz and a 40% to 60% duty cycle. |
| 8 | VCC/REF | power_in | Supply input (4.5 V minimum, 5.0 V nominal per the electrical table; absolute maximum VCC is 6.5 V) that also serves as the reference voltage input. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | SOP-8 |
| Category | Data Acquisition |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply current | ICC | | | 2 | mA | | 3 |
| Power supply | VCC | 4.5 | | | V | | 3 |
| Logical 1 input voltage (min) | VIH | 2 | | | V | VCC=5.25V | 3 |
| Logical 0 input voltage (max) | VIL | | | 0.8 | V | VCC=4.75V | 3 |
| Logical 1 input current (max) | IIH | | | 10 | µA | VIN=5.0V | 3 |
| Logical 0 input current (max) | IIL | | | -10 | µA | VIN=0V | 3 |
| Logical 1 output voltage (min) | VOH | 2.4 | | | V | VCC=4.75V, IOUT=−360 µA | 3 |
| Logical 1 output voltage (min) | VOH | 4.5 | | | V | VCC=4.75V, IOUT=−10 µA | 3 |
| Logical 0 output voltage (max) | VOL | | | 0.4 | V | VCC=4.75V, IOUT=1.6mA | 3 |
| Output source current (min) | ISOURCE | -6.5 | -14 | | mA | VOUT=0V | 3 |
| Output sink current (min) | ISINK | 8 | 16 | | mA | VOUT=VCC | 3 |
| Working clock frequency | fCLK | 10 | | 400 | kHz | | 3 |
| Conversion time | tC | 8 | | | 1/fCLK | Not including MUX addressing time | 3 |
| Clock duty cycle | | 40 | | 60 | % | | 3 |
| Data input valid after CLK rising edge (hold) | tHOLD | | | 200 | ns | | 3 |
| CLK falling edge to output data valid, MSB first | tpd1 | | | 2000 | ns | CL=100 pF, data MSB first | 3 |
| CLK falling edge to output data valid, LSB first | tpd0 | | | 1000 | ns | CL=100 pF, data LSB first | 3 |
| Rising edge of CS to data output and SAR Hi-Z | t1H,t0H | | | 400 | ns | CL=10 pF, RL=10k | 3 |
| VCC end to GND voltage | VCC | -0.5 | | 6.5 | V | VCC end to GND | 2 |
| Storage temperature | | -65 | | 150 | °C | | 2 |
| Operating ambient temperature | | -20 | | 85 | °C | | 2 |
| Welding temperature | | | | 260 | °C | 10 seconds | 2 |
| Maximum junction temperature | | | | 150 | °C | | 2 |
| Diffusion power dissipation | | | | 0.8 | W | | 2 |
| ESD (HBM) withstand voltage | | | | 4 | KV | HBM | 2 |
| Operating temperature range (ordering table) | | -20 | | 85 | °C | | 6 |
## CAD (KiCad official)
- Symbol: `XL0832DR`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `xl0832dr-etched.step` / `xl0832dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `xl0832dr.step` / `xl0832dr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [XINLUDA datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603345681667551232) (7 pp, sha256 `87c7ef837612e9ba`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/xl0832dr-datasheet.pdf)