component

XJNG0461

Public Made by Adom

by adom

WXNSIC Gate Drivers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentmotor driver icsxjng0461factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
xjng0461 / README.md
History Download
Ray Publish 0.1.0 d00dd81 8d ago

XJNG0461

WXNSIC · Gate Drivers · SOP-16

XJNG0461 from WXNSIC, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 HIN3 input Phase 3 high-side logic input; logic-high threshold is at least 2.9 V and logic-low is at most 0.4 V, with an absolute maximum of 20 V.
2 HIN2 input Phase 2 high-side logic input; logic-high threshold is at least 2.9 V and logic-low is at most 0.4 V, with an absolute maximum of 20 V.
3 HIN1 input Phase 1 high-side logic input; logic-high threshold is at least 2.9 V and logic-low is at most 0.4 V, with an absolute maximum of 20 V.
4 LIN3 input Phase 3 low-side logic input; logic-high threshold is at least 2.9 V and logic-low is at most 0.4 V, with an absolute maximum of 20 V.
5 LIN2 input Phase 2 low-side logic input; logic-high threshold is at least 2.9 V and logic-low is at most 0.4 V, with an absolute maximum of 20 V.
6 LIN1 input Phase 1 low-side logic input; logic-high threshold is at least 2.9 V and logic-low is at most 0.4 V, with an absolute maximum of 20 V.
7 GND power_in Chip ground reference for all signals and the low-side outputs; the datasheet recommends tying the logic inputs to GND when unused.
8 VDD power_out Output of the internal 5 V LDO, rated 5 V (4.7-5.3 V) at up to 40 mA for VCC 10-28 V, with an absolute maximum of 6 V and 50 mA.
9 VCC power_in Low-side supply and high-side driver reference; recommended range is 5 V to 28 V, with an absolute maximum of 40 V.
10 HO1 output Phase 1 high-side gate drive for an external P-channel MOSFET, swinging between VCC (off) and VCC-10 V (on), limited to VCC-15 V to VCC.
11 LO1 output Phase 1 low-side gate drive for an external N-channel MOSFET, swinging between GND and about 10 V (8.5-11.5 V high).
12 HO2 output Phase 2 high-side gate drive for an external P-channel MOSFET, swinging between VCC (off) and VCC-10 V (on), limited to VCC-15 V to VCC.
13 LO2 output Phase 2 low-side gate drive for an external N-channel MOSFET, swinging between GND and about 10 V (8.5-11.5 V high).
14 HO3 output Phase 3 high-side gate drive for an external P-channel MOSFET, swinging between VCC (off) and VCC-10 V (on), limited to VCC-15 V to VCC.
15 LO3 output Phase 3 low-side gate drive for an external N-channel MOSFET, swinging between GND and about 10 V (8.5-11.5 V high).
16 GND power_in Chip ground reference; a second GND pin, internally the same node as pin 7.

Key specifications

Parameter Value
Manufacturer WXNSIC
Package SOP-16
Category Motor Driver ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC VCC -0.3 40 V 5
LDO output voltage VDD -0.3 6 V 5
LDO output current IVDD -0.3 50 mA 5
Logic input voltage HIN1,2,3 and LIN1,2,3 VIN -0.3 20 V 5
Low-side output voltage LO1,2,3 VLO -0.3 15 V 5
ESD human body model ESD 2 kV 5
ESD machine model ESD 500 V 5
Package power PD 1.4 W TA ≤25°C 5
Junction-to-ambient thermal resistance RthJA 200 °C/W 5
Junction-to-case thermal resistance RthJC 40 °C/W 5
Junction temperature TJ 150 °C 5
Storage temperature TS -55 150 °C 5
Low-side supply voltage VCC VCC 5 28 V 5
LDO output current IVDD 0 40 mA VCC=10V~28V 5
LDO output current IVDD 0 50 mA VCC=11V~28V 5
Logic input ON threshold voltage HIN1,2,3 and LIN1,2,3 VIN,ON 2.9 V 5
Logic input OFF threshold voltage HIN1,2,3 and LIN1,2,3 VIN,OFF 0 0.4 V 5
Dead time between HIN1,2,3 and LIN1,2,3 inputs tDT 0.5 us 5
Input signal frequency fIN 0 50 kHz 5
Ambient temperature TA -40 125 °C 5
Logic input high-level threshold voltage VIH 2.5 V 6
Logic input low-level threshold voltage VIL 0.8 V 6
Logic '1' input bias current IIN+ 36 100 uA 6
Logic '0' input bias current IIN- 0 1 uA 6
LO high-level output voltage VLO,OH 8.5 10 11.5 V 6
VCC undervoltage positive-going threshold VCCUV+ 3.8 4.5 5 V 6
VCC undervoltage negative-going threshold VCCUV- 3.6 4.3 4.8 V 6
VCC undervoltage hysteresis VCCHYS 0.1 0.2 0.4 V 6
VCC quiescent current IQCC 0.3 0.5 1 mA 6
VDD output voltage VDD 4.7 5 5.3 V 6

CAD (KiCad official)

  • Symbol: XJNG0461
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: xjng0461-etched.step / xjng0461-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xjng0461.step / xjng0461.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: WXNSIC datasheet (11 pp, sha256 21dd9d7123c93e39, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF