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XD7650-14
Public Made by Adomby adom
XINLUDA Operational Amplifier, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownXD7650-14
XINLUDA · Operational Amplifier · DIP-14
XD7650-14 from XINLUDA, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CEXTB | passive | External nulling capacitor CEXTB connection; the capacitor (0.1µF for the internal clock) stores the correcting potential on the nulling input. |
| 2 | CEXTA | passive | External nulling capacitor CEXTA connection; the capacitor (0.1µF for the internal clock) stores the correcting potential on the nulling input. |
| 3 | NC (GUARD) | unconnected | Not connected internally; adjacent to the inverting input and usable for a guard ring to reduce leakage. |
| 4 | -IN | input | Inverting input of the amplifier; input bias current is 10pA max at +25°C. |
| 5 | +IN | input | Non-inverting input of the amplifier; input bias current is 10pA max at +25°C. |
| 6 | NC (GUARD) | unconnected | Not connected internally; adjacent to the non-inverting input and usable for a guard ring to reduce leakage. |
| 7 | V- | power_in | Negative supply; also tie INT/EXT to V- to disable the internal clock when using an external clock. |
| 8 | CRETN | passive | Capacitor return, the common connection for the two external nulling capacitors CEXTA and CEXTB. |
| 9 | OUT CLAMP | output | Output clamp; when tied to the inverting input it provides a current path to the output just before saturation to reduce overload recovery time. |
| 10 | OUTPUT | output | Amplifier output, with indefinite short-circuit duration and about 18kΩ output impedance; a 10kΩ load is needed for full swing. |
| 11 | V+ | power_in | Positive supply; operating supply range is 4.5V to 16V, with the recommended text noting 8V max for replacement use. |
| 12 | INT CLK OUT | output | Internal oscillator clock output, with a chopping frequency of about 200Hz (120Hz min to 375Hz max). |
| 13 | EXT CLK IN | input | External clock input, swinging between V+ and V- with logic threshold about 2.5V below V+, and a 50% to 80% positive duty cycle is recommended. |
| 14 | INT/EXT | input | Clock select with internal pull-up; leave open for the internal clock, or tie to V- to disable it and use an external clock. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | DIP-14 |
| Category | Amplifiers |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Offset Voltage | VOS | 0.7 | 5 | µV | +25°C | 9 | |
| Input Offset Voltage | VOS | 1 | 8 | µV | 0 to +70°C | 9 | |
| Input Bias Current | IBIAS | 4 | 10 | pA | +25°C | 9 | |
| Input Bias Current | IBIAS | 5 | 20 | pA | 0 to +70°C | 9 | |
| Input Offset Current | IOS | 8 | 20 | pA | +25°C | 9 | |
| Input Offset Current | IOS | 10 | 40 | pA | 0 to +70°C | 9 | |
| Large Signal Voltage Gain | AVOL | 135 | 150 | dB | RL = 10k, VO = 4V, +25°C | 9 | |
| Large Signal Voltage Gain | AVOL | 130 | dB | RL = 10k, VO = 4V, 0 to +70°C | 9 | ||
| Output Voltage Swing | VOUT | 4.7 | 4.85 | V | RL = 10k, +25°C | 9 | |
| Common Mode Voltage Range | CMVR | -5 | 3.5 | V | +25°C | 9 | |
| Common Mode Rejection Ratio | CMRR | 120 | 140 | dB | CMVR = -5V to +3.5V, +25°C | 9 | |
| Common Mode Rejection Ratio | CMRR | 120 | dB | CMVR = -5V to +3.5V, 0 to +70°C | 9 | ||
| Power Supply Rejection Ratio | PSRR | 120 | 140 | dB | VS = 3V to 8V, +25°C | 9 | |
| Operating Supply Range | V+ to V- | 4.5 | 16 | V | +25°C | 9 | |
| Supply Current | ISUPP | 2 | 3 | mA | No Load, +25°C | 9 | |
| Supply Current | ISUPP | 3.2 | mA | No Load, 0 to +70°C | 9 | ||
| Output Source Current | IO SOURCE | 2.9 | 4.5 | mA | +25°C | 10 | |
| Output Source Current | IO SOURCE | 2.3 | mA | 0 to +70°C | 10 | ||
| Output Sink Current | IO SINK | 25 | 30 | mA | +25°C | 10 | |
| Output Sink Current | IO SINK | 20 | mA | 0 to +70°C | 10 | ||
| Internal Chopping Frequency | fCH | 120 | 250 | 375 | Hz | Pins 13 and 14 Open, +25°C | 10 |
| Clamp ON Current | 25 | 70 | µA | RL = 100k, +25°C | 10 | ||
| Clamp OFF Current | 0.001 | 5 | nA | -4V ≤ VOUT ≤ +4V, +25°C | 10 | ||
| Clamp OFF Current | 10 | nA | -4V ≤ VOUT ≤ +4V, 0 to +70°C | 10 | |||
| Operating Temperature Range | 0 | 70 | °C | 8 | |||
| Maximum Junction Temperature (Plastic Package) | 150 | °C | 8 | ||||
| Storage Temperature Range | -55 | 150 | °C | 8 | |||
| Current to Any Pin | 10 | mA | 8 | ||||
| Input Current While Operating | 100 | µA | Note 1 | 8 | |||
| Average Temperature Coefficient of Input Offset Voltage | ΔVOS/ΔT | 0.02 | µV/°C | 0 to +70°C | 9 |
CAD (KiCad official)
- Symbol:
XD7650-14 - Footprint:
Package_DIP:DIP-14_W7.62mm - 3D model: DIP-14 (KiCad packages3D, STEP)
- 3D model files:
xd7650-14-etched.step/xd7650-14-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);xd7650-14.step/xd7650-14.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XINLUDA datasheet (16 pp, sha256
e80318dd356e2161, retrieved 2026-10-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).