component

XD7555

Public Made by Adom

by adom

XINLUDA Timers / Clock Oscillators, DIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentclock and timingxd7555factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 5h ago
viewers xd7555: viewers · Ray 5h ago
package.json Publish 0.1.0 · Ray 5h ago
page.json Set visibility: public · Ray 5h ago
README.md Publish 0.1.0 · Ray 5h ago
xd7555-etched.glb Publish 0.1.0 · Ray 5h ago
xd7555-etched.step xd7555: factory component page (tier=lcsc) · Ray 5h ago
xd7555-hero.glb xd7555: hero GLB from the etched model (keeps the MPN mark) · Ray 5h ago
xd7555-hero.overlay.json Publish 0.1.0 · Ray 5h ago
xd7555.glb Publish 0.1.0 · Ray 5h ago
xd7555.kicad_mod Publish 0.1.0 · Ray 5h ago
xd7555.kicad_sym Publish 0.1.0 · Ray 5h ago
xd7555.lbr Publish 0.1.0 · Ray 5h ago
xd7555.step Publish 0.1.0 · Ray 5h ago

XD7555

XINLUDA · Timers / Clock Oscillators · DIP-8

XD7555 from XINLUDA, in a DIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground; reference for all inputs, which must stay no lower than GND -0.3V.
2 TRIGGER input Active-low trigger input that sets the flip-flop when below 1/3 V+ (trigger voltage 28-36% VDD at 15V), dominates over THRESHOLD, and must stay within V+ +0.3V to GND -0.3V.
3 OUTPUT output CMOS inverter output that swings rail to rail, drives at least two standard TTL loads at 4.5V or more supply, with absolute maximum output current of 100mA.
4 RESET input Active-low reset input with a trip voltage of 0.4V to 1.0V at 25°C (VDD 2V to 15V) that dominates all other inputs and forces output low and discharge switch on.
5 CONTROL VOLTAGE input Control voltage input that sets the comparator trip points (about 2/3 V+, 62-71% VDD at 15V) for frequency or delay modulation, and needs no decoupling capacitor.
6 THRESHOLD input Threshold comparator input that resets the flip-flop when above 2/3 V+ (62-71% VDD at 15V), with input current of 10nA max at 25°C.
7 DISCHARGE passive Open discharge switch output that discharges the timing capacitor when the output is low, with 15mA sink at 0.4V max (VDD 5V) and leakage of 10nA max at 15V.
8 VDD power_in Positive supply with guaranteed range of 2V to 18V and an absolute maximum of +18V.

Key specifications

Parameter Value
Manufacturer XINLUDA
Package DIP-8
Category Clock and Timing
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage V+ 18 V 3
Input Voltage (Trigger, Control Voltage, Threshold, Reset) -0.3 0.3 V GND -0.3V to V+ +0.3V (max given relative to V+) 3
Output Current 100 mA 3
Operating Temperature Range -25 85 °C XL/XD7555 3
Maximum Junction Temperature (Plastic Package) 150 °C 3
Storage Temperature Range -65 150 °C 3
Thermal Resistance Junction-Ambient θJA 130 °C/W 8 Ld PDIP, typical 3
Thermal Resistance Junction-Case θJC 69 °C/W 8 Ld PDIP, typical 3
Static Supply Current IDD 40 200 µA VDD = 5V, TA=+25°C 4
Static Supply Current IDD 300 µA VDD = 5V, -55°C to +125°C 4
Static Supply Current IDD 60 300 µA VDD = 15V, TA=+25°C 4
Threshold Voltage VTH 62 67 71 % VDD VDD = 15V, TA=+25°C 4
Threshold Voltage VTH 61 72 % VDD VDD = 15V, -55°C to +125°C 4
Trigger Voltage VTRIG 28 32 36 % VDD VDD = 15V, TA=+25°C 4
Trigger Voltage VTRIG 27 37 % VDD VDD = 15V, -55°C to +125°C 4
Trigger Current ITRIG 10 nA VDD = 15V, TA=+25°C 4
Trigger Current ITRIG 50 nA VDD = 15V, -55°C to +125°C 4
Threshold Current ITH 10 nA VDD = 15V, TA=+25°C 4
Threshold Current ITH 50 nA VDD = 15V, -55°C to +125°C 4
Control Voltage VCV 62 67 71 % VDD VDD = 15V, TA=+25°C 4
Control Voltage VCV 61 72 % VDD VDD = 15V, -55°C to +125°C 4
Reset Voltage VRST 0.4 1 V VDD = 2V to 15V, TA=+25°C 5
Reset Voltage VRST 0.2 1.2 V VDD = 2V to 15V, -55°C to +125°C 5
Reset Current IRST 10 nA VDD = 15V, TA=+25°C 5
Reset Current IRST 50 nA VDD = 15V, -55°C to +125°C 5
Discharge Leakage IDIS 10 nA VDD = 15V, TA=+25°C 5
Discharge Leakage IDIS 50 nA VDD = 15V, -55°C to +125°C 5
Output Voltage Low VOL 0.4 1 V VDD = 15V, ISINK = 20mA, TA=+25°C 5
Output Voltage Low VOL 1.25 V VDD = 15V, ISINK = 20mA, -55°C to +125°C 5
Output Voltage Low VOL 0.2 0.4 V VDD = 5V, ISINK = 3.2mA, TA=+25°C 5
Output Voltage Low VOL 0.5 V VDD = 5V, ISINK = 3.2mA, -55°C to +125°C 5
Output Voltage High VOH 14.2 V VDD = 15V, ISOURCE = 0.8mA, -55°C to +125°C 5
Output Voltage High VOH 4 4.3 V VDD = 5V, ISOURCE = 0.8mA, TA=+25°C 5
Output Voltage High VOH 3.8 V VDD = 5V, ISOURCE = 0.8mA, -55°C to +125°C 5
Discharge Output Voltage VDIS 0.2 0.4 V VDD = 5V, ISINK = 15mA, TA=+25°C 5
Discharge Output Voltage VDIS 0.6 V VDD = 5V, ISINK = 15mA, -55°C to +125°C 5
Discharge Output Voltage VDIS 0.4 V VDD = 15V, ISINK = 15mA, -55°C to +125°C 5
Supply Voltage VDD 2 18 V Functional Operation, TA=+25°C 5
Supply Voltage VDD 3 16 V Functional Operation, -55°C to +125°C 5
Monostable Timing Accuracy 2 % RA = 10k, C = 0.1µF, VDD = 5V 4
Astable Timing Accuracy 2 % RA = RB = 10k, C = 0.1µF, VDD = 5V 4
Monostable Drift with Temperature 150 ppm/°C VDD = 5V, -55°C to +125°C column 4
Monostable Drift with Temperature 200 ppm/°C VDD = 10V, -55°C to +125°C column 4
Monostable Drift with Temperature 250 ppm/°C VDD = 15V, -55°C to +125°C column 4
Output Rise Time tR 75 ns RL = 10M, CL = 10pF, VDD = 5V 5
Output Fall Time tF 75 ns RL = 10M, CL = 10pF, VDD = 5V 5
Oscillator Frequency fMAX 1 MHz VDD = 5V, RA = 470Ω, RB = 270Ω, C = 200pF 5

CAD (KiCad official)

  • Symbol: XD7555
  • Footprint: Package_DIP:DIP-8_W7.62mm
  • 3D model: DIP-8 (KiCad packages3D, STEP)
  • 3D model files: xd7555-etched.step / xd7555-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xd7555.step / xd7555.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (14 pp, sha256 fe564827268b6ba8, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF