component
XD74LS95
Public Made by Adomby adom
XINLUDA Shift Registers, DIP-14. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 7d ago |
| viewers | 7d ago |
| package.json | 7d ago |
| page.json | 7d ago |
| README.md | 7d ago |
| xd74ls95-etched.glb | 7d ago |
| xd74ls95-etched.step | 7d ago |
| xd74ls95-hero.glb | 7d ago |
| xd74ls95-hero.overlay.json | 7d ago |
| xd74ls95.glb | 7d ago |
| xd74ls95.kicad_mod | 7d ago |
| xd74ls95.kicad_sym | 7d ago |
| xd74ls95.lbr | 7d ago |
| xd74ls95.step | 7d ago |
XD74LS95
XINLUDA · Shift Registers · DIP-14
XD74LS95 from XINLUDA, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SERIAL INPUT | input | Serial data input used for shift-right operation, entered when mode control is low and clock-1 makes a high-to-low transition. |
| 2 | A | input | Parallel data input A, loaded into the first flip-flop when mode control is high on the high-to-low transition of clock-2. |
| 3 | B | input | Parallel data input B, loaded into the second flip-flop when mode control is high on the high-to-low transition of clock-2. |
| 4 | C | input | Parallel data input C, loaded into the third flip-flop when mode control is high on the high-to-low transition of clock-2. |
| 5 | D | input | Parallel data input D, loaded into the fourth flip-flop when mode control is high, and the serial data input for shift-left. |
| 6 | MODE CONTROL | input | Mode control input: high selects parallel load/shift left (clock-2), low selects shift right (clock-1). |
| 7 | GND | power_in | Ground terminal, reference for all voltage values. |
| 8 | CK2 | input | Clock-2 input (L-Shift/Load), active on the high-to-low transition, used for parallel load and shift left when mode control is high. |
| 9 | CK1 | input | Clock-1 input (R-Shift), active on the high-to-low transition, used for shift right when mode control is low. |
| 10 | QD | output | Parallel output D (fourth flip-flop); IOH max -400 µA, IOL max 8 mA. |
| 11 | QC | output | Parallel output C (third flip-flop); IOH max -400 µA, IOL max 8 mA. |
| 12 | QB | output | Parallel output B (second flip-flop); IOH max -400 µA, IOL max 8 mA. |
| 13 | QA | output | Parallel output A (first flip-flop); IOH max -400 µA, IOL max 8 mA. |
| 14 | VCC | power_in | Supply voltage, recommended 4.75 V to 5.25 V (typ 5.00 V), absolute maximum 7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | DIP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage, high level | VIH | 2 | V | 3 | |||
| Input voltage, low level | VIL | 0.8 | V | 3 | |||
| Output voltage, high level | VOH | 2.7 | V | VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = -400 A | 3 | ||
| Output voltage, low level (IOL = 4 mA row) | VOL | 0.4 | V | IOL = 4 mA; VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V | 3 | ||
| Output voltage, low level (IOL = 8 mA row) | VOL | 0.5 | V | IOL = 8 mA; VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V | 3 | ||
| Input current, high level | IIH | 20 | A | VCC = 5.25 V, VI = 2.7 V | 3 | ||
| Input current, low level | IIL | -0.4 | mA | VCC = 5.25 V, VI = 0.4 V | 3 | ||
| Input current, maximum input voltage | II | 0.1 | mA | VCC = 5.25 V, VI = 7 V | 3 | ||
| Short-circuit output current | IOS | -20 | -100 | mA | VCC = 5.25 V | 3 | |
| Supply current | ICC | 13 | 21 | mA | VCC = 5.25 V | 3 | |
| Input clamp voltage | VIK | -1.5 | V | VCC = 4.75 V, IIN = -18 mA | 3 | ||
| Supply voltage | VCC | 4.75 | 5 | 5.25 | V | 3 | |
| Output current, high level | IOH | -400 | A | 3 | |||
| Output current, low level | IOL | 8 | mA | 3 | |||
| Operating temperature | Topr | -20 | 25 | 75 | C | 3 | |
| Clock frequency | fclock | 0 | 25 | MHz | 3 | ||
| Clock pulse width | tw (CK) | 20 | ns | 3 | |||
| Setup time | tsu | 20 | ns | 3 | |||
| Hold time | th | 10 | ns | 3 | |||
| Enable time 1 | tenable 1 | 20 | ns | 3 | |||
| Enable time 2 | tenable 2 | 20 | ns | 3 | |||
| Inhibit time 1 | tinhibit 1 | 20 | ns | 3 | |||
| Inhibit time 2 | tinhibit 2 | 20 | ns | 3 | |||
| Supply voltage (absolute maximum) | VCC | 7 | V | 2 | |||
| Input voltage (absolute maximum) | VIN | 7 | V | 2 | |||
| Power dissipation | PT | 400 | mW | 2 | |||
| Storage temperature | Tstg | -65 | 150 | C | 2 | ||
| Maximum clock frequency | fmax | 25 | 36 | MHz | CL = 15 pF, RL = 2 k | 3 | |
| Propagation delay time, low-to-high | tPLH | 18 | 27 | ns | 3 | ||
| Propagation delay time, high-to-low | tPHL | 21 | 32 | ns | 3 |
CAD (KiCad official)
- Symbol:
XD74LS95 - Footprint:
Package_DIP:DIP-14_W7.62mm - 3D model: DIP-14 (KiCad packages3D, STEP)
- 3D model files:
xd74ls95-etched.step/xd74ls95-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);xd74ls95.step/xd74ls95.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XINLUDA datasheet (6 pp, sha256
25d8b4583187419a, retrieved 2026-10-21, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).